Thin Film Transistor Data Line Structure for Etching Protection
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Solution Overview
Problem
The manufacturing of thin film transistor array panels faces challenges such as increased manufacturing time and cost due to the need for multiple mask processes, which can result in defects and disconnection of data lines during wet etching, particularly when forming photosensitive film patterns with copper or copper alloys.
Innovation Solution
A thin film transistor array panel design featuring a data line composed of a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, all made of the same material, with specific thickness and inclination angle differences, and a manufacturing method that involves sequential deposition and etching processes using photosensitive film patterns to minimize defects and disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to form data line and semiconductor layer, then manufacturing precision can be improved, but manufacturing time and cost increase
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by forming the data line and semiconductor layer patterns simultaneously. The single mask defines both the data line pattern and the semiconductor layer pattern in one exposure and development step, eliminating the need for separate mask processes and reducing manufacturing time while maintaining pattern precision.
Solution Approach 2:
The single mask used in the patent serves multiple functions: it defines the data line pattern, defines the semiconductor layer pattern, and acts as a protective layer during subsequent etching processes. This multi-functional approach replaces what would traditionally require multiple specialized masks, reducing both time and complexity.
2Manufacturing precision
If repeated photosensitive film pattern formation is performed on copper or copper alloy data line, then pattern precision can be improved, but data line integrity deteriorates due to disconnection
Solution Approach 1:
The patent applies a protective layer to the copper or copper alloy data line before forming the photosensitive film pattern. This protective layer is formed in advance to prevent damage during subsequent etching and processing steps, thereby maintaining data line integrity while still allowing precise pattern formation.
Solution Approach 2:
The patent introduces a protective layer as an intermediary between the copper data line and the photosensitive film/etching process. This intermediate layer protects the copper from direct exposure to harsh chemicals and mechanical stress during repeated processing, preventing disconnection while allowing precise patterning.
3Manufacturing precision
If wet etching steps are used during four mask process, then manufacturing precision can be improved, but data line disconnection risk increases
Solution Approach 1:
The patent uses a protective layer as an intermediary that shields the copper data line from direct contact with wet etching chemicals. This protective layer allows precise etching of other layers while preventing the harsh chemicals from attacking and disconnecting the copper data line.
Solution Approach 2:
The patent extracts or removes the harmful effect of wet etching on the copper data line by using the protective layer to isolate the copper from the etching environment. The etching process can proceed with high precision on other layers without the harmful side effect of copper corrosion or disconnection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and minimizes damage to the data line during etching, enhancing the reliability and efficiency of the manufacturing process while maintaining the integrity of the data line, thereby reducing manufacturing time and cost.
Implementation Method 1
The upper data layer and the buffer layer may be sequentially deposited
Data Source
AI summary
A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.