TFT Placement Between Data Lines to Reduce RC Delay
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Solution Overview
Problem
Organic electroluminescent display devices face challenges in reducing resistance-capacitance (RC) delay, which affects data writing time and image quality, especially as display panels increase in size.
Innovation Solution
The arrangement of data lines and thin-film transistors (TFTs) is optimized such that the first TFT is located between successive data lines, reducing parasitic capacitance and minimizing RC delay by preventing unwanted overlap between the TFT's active layer and data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data lines are arranged close to pixels to reduce wiring complexity, then device complexity is reduced, but parasitic capacitance increases causing RC delay
Solution Approach 1:
The patent extracts the problematic overlap region by positioning the TFT between successive data lines, separating the TFT's active layer from direct overlap with data lines. This reduces parasitic capacitance between the active layer and data lines, thereby reducing RC delay while maintaining the compact data line arrangement close to pixels.
Solution Approach 2:
The patent changes the spatial arrangement from a conventional layout to a three-dimensional configuration where data lines are successively positioned at different locations, and the TFT is strategically placed between them. This dimensional reorganization reduces parasitic capacitance without increasing wiring complexity.
2Reliability
If TFT is positioned to couple pixel to data line, then electrical connection is established, but parasitic capacitance is generated between TFT's active layer and data lines
Solution Approach 1:
The patent converts the potentially harmful parasitic capacitance into a beneficial configuration by positioning the TFT between successive data lines. This arrangement reduces unwanted capacitance between the active layer and data lines, while the TFT still effectively couples the pixel to the appropriate data line for data writing.
3Productivity
If display panel size increases to meet market demand, then productivity is improved, but RC delay increases affecting image quality
Solution Approach 1:
The patent applies local quality optimization by specifically addressing the RC delay problem in larger display panels through strategic TFT positioning. The TFT is placed between successive data lines in regions where data writing occurs, locally reducing parasitic capacitance and RC delay, thereby maintaining fast data writing speeds even as overall display size increases.
Data Source
AI summary
An organic electroluminescent display device including a plurality of scan lines and a plurality of data lines crossing the scan lines, a plurality of pixels at regions defined by the scan lines and the data lines, and one or more thin-film transistors (TFTs) for selectively applying voltages to each of the pixels, wherein the data lines are successively located at a side of the pixels, and a first TFT of the TFTs is located at least partially between an area corresponding to an nth data line of the data lines and an area corresponding to an (n−1)th data line of the data lines, the nth data line and the (n−1)th data line being successively positioned.