TFT Delay Inverter Layout for Stable Low-Power Signal Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In polysilicon or amorphous silicon processes for TFTs on insulating substrates, variations in transistor characteristics like threshold voltage and mobility lead to increased power consumption and larger transistor sizes, making it difficult to achieve low power consumption and a narrow frame in display devices.
Innovation Solution
A delay circuit with a series and parallel configuration of transistors of identical and different channel types, along with a hysteresis characteristic generating circuit, allows for signal delay and control signal generation based on transistor characteristics, reducing power consumption and frame size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If typical CMOS inverter circuits are used for delay buffer, then the circuit configuration is simple and power consumption is low, but the delay amount varies greatly depending on transistor characteristics variations
Solution Approach 1:
The delay buffer is divided into multiple delay units, each consisting of a specific number of inverter circuits. By segmenting the total delay requirement into manageable units and selecting an appropriate number of units, the circuit achieves both simplicity and stable delay performance despite transistor characteristic variations.
Solution Approach 2:
The patent applies different channel types (N-channel and P-channel) to different transistor positions within the delay buffer. Specifically, transistors at different locations have different channel types to compensate for characteristic variations, with the number of transistors of each channel type carefully selected to achieve stable delay performance.
2Reliability
If transistor size is increased to accommodate characteristic variations, then reliability improves, but power consumption increases and frame size increases
Solution Approach 1:
The patent changes the channel type parameter of transistors at different positions within the delay buffer rather than uniformly increasing transistor size. By selecting transistors with different channel types (N-channel or P-channel) based on their position, the circuit achieves characteristic variation compensation without increasing overall power consumption or frame size.
3Reliability
If transistor size is increased to accommodate characteristic variations, then reliability improves, but frame size increases
Solution Approach 1:
Instead of increasing transistor size, the patent changes the channel type parameter of transistors based on their position in the delay buffer. This approach maintains compact transistor dimensions while achieving reliable delay performance through the strategic selection of N-channel and P-channel transistors in different positions.
4Difficulty of detecting and measuring
If delay amount is used to detect transistor characteristics, then measurement is simplified, but accuracy decreases due to large dependency on both Nch and Pch transistors
Solution Approach 1:
The delay buffer is segmented into multiple delay units with specific numbers of inverter circuits. By measuring the delay of each segment and analyzing the combined delay characteristics, the patent achieves accurate transistor parameter detection while maintaining simple measurement procedures.
Solution Approach 2:
The patent uses the different channel types at different positions to isolate and detect specific transistor characteristics. By analyzing the delay contribution of transistors with different channel types in specific positions, the measurement system achieves higher precision in detecting transistor parameters.
Data Source
AI summary
Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.