Thin Film Transistor Dielectric Stack via Selective ALD
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Solution Overview
Problem
Current methods for patterning and forming high-quality dielectric layers in thin film transistors are limited by the need for thick single layers or complex multilayer stacks, which are time-consuming and difficult to process, especially when using flexible plastic substrates, and there is a lack of efficient methods for combining multiple selective area deposition steps to form functional devices.
Innovation Solution
The use of selective area deposition combined with atomic layer deposition, employing a deposition inhibitor material to pattern inorganic thin film dielectric layers, allowing for the creation of multi-layer dielectric stacks with precise control over critical interfaces, enabling the formation of high-quality dielectric layers on flexible substrates without the need for thick single layers or complex equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick single dielectric layers are used to ensure adequate insulation and device performance, then reliability is improved, but manufacturing complexity and processing time increase
Solution Approach 1:
The patent divides a thick dielectric layer into multiple thin sequential layers (first inorganic thin film dielectric layer, second inorganic thin film dielectric layer, third inorganic thin film dielectric layer). Each layer is deposited separately using atomic layer deposition (ALD) with precise control over thickness and composition, enabling adequate insulation performance while simplifying processing and improving manufacturability
2Manufacturing precision
If traditional photolithography is used for patterning on plastic substrates, then manufacturing precision can be achieved, but the process is limited by substrate temperature constraints and dimensional stability
Solution Approach 1:
The patent replaces traditional photolithography (which relies on photochemical reactions and mechanical processing) with atomic layer deposition (ALD) for patterning. The ALD process uses vapor-phase precursor deposition at low temperatures, eliminating the need for high-temperature processing and solvent-based development that plague plastic substrate fabrication. This substitution enables precise patterning on flexible plastic substrates without temperature or dimensional stability constraints
3Reliability
If complex multilayer dielectric stacks are formed to achieve desired electrical properties, then device performance is improved, but processing time and manufacturing cost increase
Solution Approach 1:
The patent combines multiple dielectric layers (first, second, and third inorganic thin film dielectric layers) into an integrated multilayer stack structure that achieves desired electrical properties in a single coordinated fabrication sequence. By using atomic layer deposition for all layers and integrating the patterning process, the patent reduces total processing time and manufacturing cost compared to forming complex multilayer stacks through separate conventional processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of thin film transistors with improved performance and reduced processing time, allowing for cost-effective and efficient manufacturing of flexible electronic devices by patterning inorganic thin film dielectric layers on flexible substrates, enhancing device yield and functionality.
Implementation Method 1
selective area deposition combined with atomic layer deposition, employing a deposition inhibitor material to pattern inorganic thin film dielectric layers
Implementation Method 2
atomic layer deposition, employing a deposition inhibitor material to pattern inorganic thin film dielectric layers
Data Source
AI summary
A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack.