Thin Film Transistor Fabrication Using Diffraction Exposure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional method for fabricating thin film transistors in LCD devices requires an 8-mask process, which increases fabrication costs, processing time, and defect generation, and is not cost-competitive due to the complexity and number of mask processes, and also risks losing the n+ doped ohmic contact layer during semiconductor layer contact hole formation in top-gate structures.
Innovation Solution
A 6-mask process is introduced using diffraction exposure to pattern source/drain and active regions, reducing the number of mask processes and simplifying the fabrication by etching these regions using diffraction-exposure and PR ashing, thereby forming the LDD layer and inter-insulating layer, which reduces the complexity and cost of the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an 8-mask process is used to fabricate thin film transistors, then the fabrication process can be completed with conventional methods, but the fabrication cost increases, processing time increases, and defect generation increases
Solution Approach 1:
The patent combines multiple mask processes into fewer steps by using self-aligned fabrication techniques. Specifically, the gate electrode pattern serves as a self-aligned mask for forming the semiconductor layer patterns, eliminating the need for separate alignment masks and reducing the total number of mask processes from 8 to 6 or fewer steps.
Solution Approach 2:
The patent performs preliminary patterning of the gate electrode layer before forming the semiconductor layer. This preliminary action establishes the gate pattern that will automatically serve as the alignment reference for subsequent semiconductor layer formation, eliminating the need for complex alignment procedures and reducing mask process steps.
2Reliability
If an 8-mask process is used to fabricate thin film transistors, then conventional fabrication methods can be applied, but processing time increases
Solution Approach 1:
The patent merges multiple fabrication steps into fewer process stages. By using the gate electrode pattern as a self-aligned mask, the patent combines what would traditionally require separate alignment and patterning steps into a single integrated process, reducing the total number of mask processes and associated processing time.
Solution Approach 2:
The gate electrode pattern serves its dual function as both the functional electrode and as the alignment mask for subsequent layers. This self-service approach eliminates the need for separate alignment masks and reduces the number of photolithography cycles, thereby reducing processing time.
3Reliability
If an 8-mask process is used to fabricate thin film transistors, then conventional methods can be used, but defect generation increases
Solution Approach 1:
The patent combines multiple patterning steps into fewer integrated steps using self-alignment. This reduction in the number of mask processes decreases the cumulative probability of defects that can occur during repeated photolithography cycles, including alignment errors, photoresist contamination, and etch variability.
Solution Approach 2:
The gate electrode pattern automatically serves as the alignment reference for semiconductor layer patterning, eliminating alignment errors that would occur with separate masks. This self-aligned approach ensures precise positioning without the defects associated with manual or mechanical alignment procedures.
4Shape
If a top-gate structure is used with conventional fabrication, then the transistor structure can be formed, but the n+ doped ohmic contact layer is lost during semiconductor layer contact hole formation
Solution Approach 1:
The patent performs preliminary doping to form the ohmic contact layer in the semiconductor layer before forming contact holes. This preliminary action ensures that the ohmic contact regions are already doped with appropriate conductivity before any etching or hole formation steps, preventing loss of the doped layer during subsequent processing.
Solution Approach 2:
The patent combines the doping step with the semiconductor layer formation step, creating a self-aligned structure where the doped regions are automatically positioned. This integrated approach ensures that the n+ doped ohmic contact layer remains intact and properly positioned during contact hole formation, as the doping occurs before any etching that might remove the layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 6-mask process reduces the number of mask processes, decreases fabrication costs, improves production yield, and minimizes defects by simplifying the fabrication steps and maintaining the integrity of the n+ doped ohmic contact layer, enhancing the overall efficiency and cost-effectiveness of the thin film transistor production.
Implementation Method 1
a third photoresist pattern defining source/drain and active regions is formed by a diffraction exposure
Data Source
AI summary
A method for fabricating a thin film transistor for an LCD device is presented that uses six mask processes. Portions of a semiconductor layer formed on a substrate are doped with first and second impurities in different regions. A conductive layer is deposited and the conductive and semiconductor layers patterned together by diffraction exposure using a diffraction pattern mask to define source and drain regions and an activate region. Ashing is performed and portions of the conductive layer removed to form the source, drain and channel. A gate insulating layer is formed on the substrate and gates are formed on the gate insulating layer. A passivation film is formed on the substrate and a pixel contact hole exposing one of the drains is etched. A pixel electrode is then deposited such that the pixel electrode is connected to the drain through the pixel contact hole.