TFT Display Barrier Layer for Parasitic Capacitance Reduction
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Solution Overview
Problem
Display devices with light-scattering layers experience increased parasitic capacitance between major signal lines and the cathode, leading to signal delays and reduced signal quality due to reduced distances and exposure to light and hydrogen.
Innovation Solution
Incorporating a barrier layer between major signal lines and the cathode, along with a contact hole through the planarization and insulating layers, to reduce parasitic capacitance and block light and hydrogen.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a light-scattering layer structure including quantum dots is used to improve color reproducibility and luminous efficiency, then display quality is improved, but parasitic capacitance between major signal lines and cathode is increased causing signal delays
Solution Approach 1:
A barrier layer is introduced as an intermediary component between the major signal lines and the cathode. This barrier layer serves as a mediating structure that reduces parasitic capacitance while allowing the light-scattering layer to maintain its display quality functions. The barrier layer acts as a buffer that prevents direct capacitive coupling between the signal lines and cathode, thereby reducing signal delays without compromising display performance.
2Device complexity
If the distance between major signal lines and cathode is reduced to improve device integration, then device complexity is reduced, but parasitic capacitance is increased causing signal delays
Solution Approach 1:
The barrier layer serves as a mediating structure that enables close integration between signal lines and cathode while preventing excessive parasitic capacitance. By positioning the barrier layer between these components, the design achieves high device integration with minimal signal delay, as the barrier layer manages the electromagnetic interaction without requiring increased spacing.
3Reliability
If a barrier layer is introduced to reduce parasitic capacitance and block light and hydrogen, then signal integrity is improved, but device complexity is increased
Solution Approach 1:
The barrier layer is designed to perform multiple functions simultaneously: it reduces parasitic capacitance between signal lines and cathode, blocks light from reaching the cathode, and prevents hydrogen diffusion. By consolidating these three protective functions into a single layer, the design improves signal integrity without proportionally increasing device complexity, as one layer accomplishes what would otherwise require multiple separate components.
4Reliability
If contact holes are introduced to electrically connect the barrier layer to the first electrode pattern, then signal transmission is stabilized, but manufacturing complexity is increased
Solution Approach 1:
The electrical connection path is segmented into discrete components: the barrier layer, the planarization layer with contact holes, and the first electrode pattern. The contact holes create distinct electrical pathways that allow the barrier layer to be electrically connected to the electrode pattern while maintaining physical separation. This segmentation enables stable signal transmission through defined connection points while allowing standard semiconductor manufacturing processes to be used.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes parasitic capacitance, stabilizes signal transmission, and enhances display quality by maintaining consistent signal integrity and reducing hydrogen-induced degradation.
Implementation Method 1
block light from above and hydrogen by introducing a barrier layer on a thin-film transistor (TFT)
Implementation Method 2
block light from above and hydrogen by introducing a barrier layer on a thin-film transistor (TFT)
Implementation Method 3
reduce delays in signals by reducing parasitic capacitance by introducing a barrier layer between major signal lines and the cathode
Data Source
AI summary
A display device includes a thin-film transistor disposed on a substrate including an active layer, a gate electrode, a first electrode pattern, and a second electrode pattern; an insulating layer is disposed on the thin-film transistor; a barrier layer is disposed on the insulating layer; a planarization layer is disposed on the barrier layer; and a first electrode is disposed on the planarization layer, wherein the barrier layer is electrically connected to the first electrode pattern through the first electrode.


