Thin Film Transistor Display Gate Wire with Variable Thickness
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Solution Overview
Problem
As the surface area of flat panel displays increases, signal lines become longer, leading to increased resistance and power consumption, which can result in signal delay or voltage drop, necessitating the use of low-resistance materials for signal lines.
Innovation Solution
The thin film transistor display panel incorporates signal lines with large cross-sectional areas and a manufacturing method that forms gate and data wire lines with varying thicknesses, using materials like aluminum or silver-based metals, and employs electroless plating to maintain resistance while preventing surface roughness, with blocking layers controlling the growth of layers during plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signal lines are made longer to increase display surface area, then display size is improved, but resistance and power consumption increase
Solution Approach 1:
The patent applies local quality by forming gate wire lines with non-uniform thickness: thicker in the first region (where gate lines are positioned) and thinner in the second region (where gate electrodes are positioned). This localized thickness variation reduces resistance in the gate line extension direction without increasing overall power consumption, thereby resolving the contradiction between display size expansion and energy loss.
Solution Approach 2:
The patent changes the physical parameter of wire line thickness to reduce resistance. By increasing the thickness of gate wire lines in specific regions, the resistance is reduced, which directly addresses the power consumption issue arising from longer signal lines in larger displays.
2Loss of energy
If wire line thickness is increased to reduce resistance, then resistance is improved, but surface roughness increases
Solution Approach 1:
The patent uses local quality by selectively forming thicker wire lines only in the first region (gate line region) where resistance reduction is needed, while maintaining thinner thickness in the second region (gate electrode region). This localized approach reduces resistance without causing excessive surface roughness across the entire display surface.
Solution Approach 2:
The gate wire line structure is segmented into two distinct regions with different thicknesses. The first region has greater thickness for resistance reduction, while the second region has lesser thickness to maintain surface quality. This segmentation allows the patent to address resistance issues locally without compromising overall surface roughness.
3Loss of energy
If uniform thick wire lines are formed to reduce resistance, then resistance is improved, but TFT channel formation reliability decreases
Solution Approach 1:
The patent applies local quality by forming thicker gate wire lines only in the first region and thinner lines in the second region where gate electrodes are positioned. This localized thickness control ensures that TFT channel formation is not adversely affected by excessive thickness variations, while still achieving resistance reduction in the gate line regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and power consumption by selectively forming thick wire lines only on specific regions, maintaining reliable TFT channel formation and preventing increased surface roughness, thus enhancing the performance of flat panel displays.
Implementation Method 1
employs electroless plating to maintain resistance while preventing surface roughness
Data Source
AI summary
A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.