TFT Source-Drain Dopant Profile Control
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Solution Overview
Problem
Existing TFT manufacturing processes result in source and drain regions with high dopant concentration gradients, leading to increased electric fields and performance degradation, such as the 'kink' effect and leakage current, due to the use of abrupt junctions and non-self-aligned processes which are not reproducible and costly.
Innovation Solution
A process forming a doped amorphous silicon layer with a controlled gradual dopant profile is achieved by selectively removing the heavily doped layer using a photoresist development solution, allowing for a diffusion and activation step that maintains low electric field values next to the channel region, avoiding high-temperature diffusion steps that damage glass substrates and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ionic implantation is used to form source and drain regions, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent removes the ionic implantation step from the manufacturing process, replacing it with a simpler photolithographic etching process to form the doped amorphous silicon layer. This extraction of the complex implantation step reduces device complexity while maintaining dopant profile control through the photoresist development solution method.
2Manufacturing precision
If conventional diffusion step is used to realize source-drain regions, then manufacturing precision is improved, but the glass substrate is damaged due to high temperature
Solution Approach 1:
The patent changes the temperature parameter from high-temperature conventional diffusion to low-temperature photolithographic etching followed by controlled dopant diffusion. This parameter change allows source-drain region formation without damaging the glass substrate, as the process occurs at temperatures compatible with glass substrate integrity.
3Manufacturing precision
If abrupt junction type source-drain regions are formed, then manufacturing precision is improved, but electric performance deteriorates due to high electric fields
Solution Approach 1:
The patent applies local quality by creating a gradual dopant concentration profile in the source and drain regions adjacent to the channel, rather than an abrupt junction. This localized gradual transition reduces high electric fields in critical regions while maintaining precise dopant placement through the photolithographic masking method, thereby improving electric performance without sacrificing manufacturing precision.
4Ease of manufacture
If non-self-aligned process is used, then ease of manufacture is improved, but manufacturing precision deteriorates due to non-reproducibility
Solution Approach 1:
The patent implements a self-aligned process where the photoresist mask automatically defines both the gate electrode position and the source-drain region boundaries. The photoresist development solution selectively removes the doped amorphous silicon layer in a self-aligned manner, eliminating the need for separate alignment steps. This self-service approach maintains ease of manufacture while achieving high alignment precision and reproducibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process ensures reproducible TFT devices with improved electric performance by minimizing the 'kink' effect and leakage current, maintaining low electric fields, and enhancing the industrial scalability of TFT production by using a low-temperature doped layer formation and selective etching.
Implementation Method 1
selectively removing the heavily doped layer using a photoresist development solution
Implementation Method 2
carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer into said amorphous silicon layer
Data Source
AI summary
A process for realizing TFT devices on a substrate comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device.