Thin-Film Transistor Doping Structure for Leakage Current Suppression
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Solution Overview
Problem
Display apparatuses face issues in displaying high-quality images due to the occurrence of leakage currents in thin film transistors.
Innovation Solution
A thin film transistor design is implemented, featuring a semiconductor layer with specific doping areas and a buffer layer, which minimizes leakage current by creating a barrier with a steep slope and restricting the leakage current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional thin film transistor structure is used, then the device complexity is low, but leakage current occurs affecting image quality
Solution Approach 1:
The semiconductor layer is segmented into multiple doped regions (first area, second area, third area, fourth area) with different conductivity types and doping concentrations. This segmentation creates distinct functional zones that control carrier distribution and form barriers to leakage current paths, resolving the contradiction by dividing the semiconductor layer into specialized regions rather than using a uniform structure
Solution Approach 2:
Different regions of the semiconductor layer are assigned different local qualities through selective doping: the first and second areas have high doping concentrations of first conductivity type near the upper surface, while the third and fourth areas have doping of second conductivity type at deeper levels. This local quality variation creates steep slope barriers at interfaces, effectively blocking leakage current while maintaining device functionality
2Reliability
If the semiconductor layer uses uniform doping, then the manufacturing process is simple, but leakage current paths form between source and drain
Solution Approach 1:
The doping process is segmented into multiple steps targeting different regions: first and second areas receive first conductivity type dopants, while third and fourth areas receive second conductivity type dopants. This segmented doping approach, though more complex than uniform doping, creates the necessary steep slope barriers to suppress leakage current
Solution Approach 2:
The doping structure extends into the depth dimension of the semiconductor layer, with first areas and second areas positioned near the upper surface and third areas and fourth areas positioned at deeper levels. This vertical dimensionality creates steep slope barriers that block leakage current paths without requiring excessive lateral complexity in the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces leakage current levels, enhancing the display apparatus's ability to produce high-quality images with reduced image quality degradation.
Implementation Method 1
the semiconductor layer includes a first area doped with a first conductivity type and disposed adjacent to an upper surface of the semiconductor layer, a second area spaced apart from the first area, doped with the first conductivity type, and disposed adjacent to the upper surface of the semiconductor layer, a third area doped with a second conductivity type different from the first conductivity type and disposed under the first area, and a fourth area doped with the second conductivity type and disposed under the second area
Data Source
AI summary
Provided are a thin film transistor capable of minimizing the level of a leakage current and a display apparatus including the same. The thin film transistor includes a buffer layer disposed over a substrate, and a semiconductor layer disposed over the buffer layer, wherein the semiconductor layer includes a first area doped with a first conductivity type and disposed adjacent to an upper surface of the semiconductor layer, a second area spaced apart from the first area, doped with the first conductivity type, and disposed adjacent to the upper surface of the semiconductor layer, a third area doped with a second conductivity type different from the first conductivity type and disposed under the first area, and a fourth area doped with the second conductivity type and disposed under the second area.