Thin Film Transistor Double Semiconductor Layer Low Voltage Driving
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Solution Overview
Problem
Conventional thin film transistors face challenges in achieving high-speed driving due to low carrier mobility in amorphous silicon and non-uniform threshold voltage in polycrystalline silicon, while oxide semiconductors offer improved characteristics but require innovative structural designs for efficient low-voltage operation.
Innovation Solution
A thin film transistor design featuring a double-semiconductor layer structure with a lower and upper gate electrode, where the first and second semiconductor layers can be made of amorphous silicon, oxide semiconductor, or nitride semiconductor, and a passivation layer, enabling effective carrier injection and low-voltage driving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as the active layer, then the manufacturing process is simple and low-temperature processing is enabled, but carrier mobility is low resulting in difficulty achieving high-speed driving
Solution Approach 1:
The patent employs a composite semiconductor structure combining amorphous silicon and oxide semiconductor layers. The amorphous silicon layer provides ease of manufacturing and low-temperature processing, while the oxide semiconductor layer contributes high carrier mobility for high-speed driving, thus resolving the contradiction between manufacturing simplicity and driving speed.
Solution Approach 2:
The active layer is segmented into multiple functional layers: a lower amorphous silicon layer for easy manufacturing and an upper oxide semiconductor layer for high carrier mobility. This segmentation allows each layer to fulfill its specific function, achieving both simple manufacturing and high-speed driving capability.
2Speed
If polycrystalline silicon is used as the active layer, then carrier mobility is high enabling high-speed driving, but threshold voltage is non-uniform affecting device consistency
Solution Approach 1:
The patent uses a composite structure where the oxide semiconductor layer provides high carrier mobility for high-speed driving, while the amorphous silicon layer and carefully controlled oxide semiconductor composition ensure uniform threshold voltage. This composite approach achieves both high speed and device consistency.
Solution Approach 2:
The oxide semiconductor layer is specifically engineered with controlled composition and structure to provide high carrier mobility in the channel region while maintaining uniform electrical characteristics. The local optimization of the oxide semiconductor layer properties ensures both high-speed performance and threshold voltage uniformity.
3Speed
If oxide semiconductor is used as the active layer, then high carrier mobility and excellent electric characteristics are achieved, but additional structural design complexity is required for low-voltage operation
Solution Approach 1:
The device is segmented into distinct functional regions including a lower gate electrode for carrier injection, an upper gate electrode for channel control, and multiple semiconductor layers with specific functions. This segmentation allows the oxide semiconductor to achieve high carrier mobility while the structured design manages the complexity through clear functional separation.
Solution Approach 2:
The patent introduces a vertical stacking dimension with multiple gates and semiconductor layers, transforming the conventional planar structure into a three-dimensional architecture. This dimensional change enables low-voltage operation through enhanced electric field control while accommodating the oxide semiconductor's high mobility characteristics.
Data Source
AI summary
A thin film transistor includes: a lower gate electrode on a substrate; a gate insulating layer on the lower gate electrode; a first semiconductor layer on the gate insulating layer; a source electrode on the first semiconductor layer, a drain electrode on the first semiconductor layer and spaced apart form the source electrode; a second semiconductor layer on a channel region of the first semiconductor layer and on the source electrode and the drain electrode; a passivation layer on the second semiconductor layer; and an upper gate electrode disposed on the passivation layer, corresponding to the channel region.