Thin Film Transistor Drain Electrode Non-Overlap Design
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Solution Overview
Problem
Conventional thin film transistors in liquid crystal displays suffer from a feed-through effect due to coupling capacitance, which can be exacerbated by increased storage capacitors, leading to reduced aperture ratio and potential issues like short mura and flicker, especially when there are misalignment or etching unevenness problems.
Innovation Solution
A thin film transistor array substrate design where the drain electrode does not overlap the gate electrode, incorporating a light shielding layer to prevent leakage and reduce coupling capacitance, and a semiconductor layer with a doped layer to enhance electrical connections and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage capacitor is increased to reduce feed-through effect, then the coupling capacitance effect is reduced, but the aperture ratio is reduced
Solution Approach 1:
The patent extracts and removes the overlapping portion of the drain electrode that would otherwise overlap with the gate electrode. This is achieved by introducing a light shielding layer that is selectively removed to create an opening, allowing the drain electrode to be formed without overlapping the gate electrode, thereby reducing coupling capacitance without requiring additional capacitor area
Solution Approach 2:
The light shielding layer serves as an intermediary element during the fabrication process. It temporarily occupies the space where the drain electrode would overlap with the gate electrode, and is subsequently removed to create the necessary opening, enabling the drain electrode to be positioned without coupling capacitance issues
2Reliability
If exposure misalignment or etching unevenness occurs, then coupling capacitance generates short mura or flicker, but these problems can be eliminated by reducing coupling capacitance
Solution Approach 1:
The patent applies preliminary anti-action by designing the drain electrode structure to not overlap with the gate electrode from the outset. This preventive design eliminates the coupling capacitance that would otherwise cause short mura and flicker, making the display quality insensitive to exposure misalignment and etching unevenness
Solution Approach 2:
The light shielding layer is formed and patterned in advance during the fabrication process, creating a template that guides the subsequent formation of the drain electrode. This preliminary action ensures that the drain electrode is automatically positioned without overlapping the gate electrode, preventing coupling capacitance issues before they can occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces coupling capacitance by 80% and minimizes leakage current, improving the overall performance and reliability of the liquid crystal display by eliminating feed-through effects and enhancing the transistor's electrical properties.
Implementation Method 1
The light shielding layer is etched using the patterned doped semiconductor layer as a mask, wherein the etched light shielding layer is used for shielding a portion of the semiconductor layer from the light
Implementation Method 2
A gate electrode 102 overlaps a source electrode 106 and a drain electrode 104, such that a coupling capacitance Cgd occurs between the gate electrode 102 and the drain electrode 104
Implementation Method 3
A doped semiconductor layer is formed on the semiconductor layer
Data Source
AI summary
A thin film transistor array substrate is disclosed. A gate electrode is disposed overlying a substrate. A gate dielectric layer covers the substrate and the gate electrode. A semiconductor layer is disposed overlying the gate dielectric layer, wherein the semiconductor layer comprises a channel. A source electrode electrically connects a portion of the semiconductor layer on one side of the channel, and a drain electrode electrically connects a portion of the semiconductor layer on the other side of the channel, in which the drain electrode does not overlap the gate electrode.