TFT Drain Gate Overlap Area for LCD Brightness Uniformity
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Solution Overview
Problem
Conventional liquid crystal displays (LCDs) experience flickering and uneven brightness due to electrical resistance in power lines, causing voltage drops and capacitive coupling effects, especially at locations farther from the signal input, leading to inconsistent display effects.
Innovation Solution
The solution involves adjusting the parasitic capacitance (Cgd) by increasing the projection area of the drain on the gate in thin film transistors (TFTs) along the direction away from the scanning controller, which balances the capacitive coupling effect and maintains display consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional driving method is used in large-sized high-resolution panel, then manufacturing is simpler, but flickering screen and uneven brightness occur due to voltage drop along power lines
Solution Approach 1:
The patent applies local quality by differentiating the parasitic capacitance values of TFTs based on their positions in the display panel. TFTs closer to the scanning controller have smaller parasitic capacitance, while those farther away have larger parasitic capacitance. This localized differentiation compensates for voltage drops along the power lines, ensuring uniform brightness across the entire panel without changing the overall manufacturing process.
Solution Approach 2:
The patent changes the electrical parameter (parasitic capacitance) of the TFTs by adjusting the overlapping area between the gate and drain electrodes. By controlling the geometric dimensions of these electrodes during fabrication, the parasitic capacitance is tuned to specific values that compensate for position-dependent voltage drops, thereby resolving the display uniformity issue while maintaining conventional manufacturing methods.
2Reliability
If parasitic capacitance is increased for TFTs farther from scanning controller, then display uniformity improves, but device structure becomes more complex
Solution Approach 1:
The patent achieves the desired parasitic capacitance values by adjusting geometric parameters (overlapping area dimensions) of existing TFT components rather than introducing new structural elements. This approach modifies electrical characteristics through dimensional changes in the gate-drain overlap region, avoiding additional device complexity while achieving display uniformity.
3Reliability
If voltage drop along power line is compensated by increasing parasitic capacitance, then capacitive coupling effect is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a systematic local quality strategy where the overlapping area dimensions are pre-calculated for different positional groups of TFTs. This allows manufacturers to apply different but well-defined dimensional specifications to different regions, making the precision requirements manageable through standardized local parameters rather than requiring complex real-time adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces voltage drops and enhances display uniformity, improving the brightness consistency and overall display quality of the LCD.
Implementation Method 1
a stacked area of the drain and the gate in the third direction is a rectangle... By stacking the other end of the drain and the gate to form the projection area, the parasitic capacitance is formed
Implementation Method 2
The voltage (Vp) on the pixel electrode changes due to the capacitive coupling effect
Data Source
AI summary
The present disclosure relates to a liquid crystal display (LCD) having a substrate and at least one scanning controller. the substrate is configured with a plurality of thin film transistors (TFTs). Each of the TFTs includes a gate, a drain and a pixel electrode, and the gate of each of the TFTs electrically connecting to the scanning controller along a first direction in sequence. One end of the drain connects to the pixel electrode, and the other end of the drain is stacked on the gate along a third direction perpendicular to the substrate. The drain is insulated from the gate, and a dimension of a projection area of the drain on the gate along the third direction increases when a distance between the TFT and the scanning controller in the first direction increases.