TFT Drain Electrode Layout for Uniform Pixel Gate Capacitance
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Solution Overview
Problem
In liquid crystal display (LCD) devices, process variations during manufacturing can lead to non-uniform parasitic capacitance across pixels, causing kickback voltage variations and resulting in uneven display quality due to overlapping areas between gate and source/drain electrodes.
Innovation Solution
The design incorporates a drain electrode with a bar-shaped portion on a semiconductor pattern, a compensation portion, a connecting portion, and a pad portion, where the bar-shaped portion has a specific width and the compensation and connecting portions have a wider width than the bar-shaped portion, ensuring uniform gate capacitance across pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode partially overlaps the source electrode and drain electrode to form parasitic capacitance, then the TFT can be driven properly, but the parasitic capacitance causes kickback voltage and affects data signal quality
Solution Approach 1:
The drain electrode is designed with different width characteristics in different regions: a first width in the overlapping region with the gate electrode and a second width in non-overlapping regions. This local variation in geometric properties allows the electrode to serve dual functions - maintaining necessary parasitic capacitance for TFT operation while controlling the magnitude of kickback voltage by reducing the width in critical overlapping areas.
Solution Approach 2:
The invention changes the geometric parameter (width) of the drain electrode along its length. By varying the width parameter from the first width to the second width in different sections, the patent optimizes the electrical characteristics - specifically balancing the parasitic capacitance needed for proper TFT switching with the kickback voltage that must be minimized to preserve data signal integrity.
2Ease of manufacture
If process variation occurs during manufacturing, then production flexibility is maintained, but overlap areas between gate electrode and source/drain electrodes vary causing non-uniform parasitic capacitance across pixels
Solution Approach 1:
The compensation portion of the drain electrode is designed to create equivalent electrical characteristics across different pixels. By adding this additional electrode section with specific width and positioning, the invention compensates for variations in overlap areas caused by process tolerances, ensuring that all pixels achieve substantially the same total parasitic capacitance value despite manufacturing variations in the main overlapping regions.
Solution Approach 2:
The invention introduces an additional geometric parameter (the compensation portion with its own width and length) that can be adjusted to counterbalance variations in other parameters. This allows the design to maintain uniform electrical performance across the display panel even when process variations cause differences in the primary overlap dimensions.
3Ease of manufacture
If parasitic capacitance varies across pixels due to process variation, then manufacturing remains simple, but kickback voltage varies according to pixel location resulting in non-uniform display quality
Solution Approach 1:
The compensation portion is strategically positioned and dimensioned to provide localized capacitance adjustment. This local modification approach allows uniform display quality to be achieved across all pixels without requiring complex global process controls, maintaining manufacturing simplicity while correcting for process variations through targeted geometric adjustments in the electrode design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains consistent gate capacitance even with process variations, ensuring uniform display quality by compensating for capacitance differences across pixels.
Implementation Method 1
A parasitic capacitance generated in an overlapping portion between the gate electrode and the source electrode, and the gate electrode and the drain electrode may cause a kickback voltage and affect a data signal
Data Source
AI summary
A display device is provided. A display device includes a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed to overlap the gate electrode; a source electrode disposed on the semiconductor pattern; a drain electrode disposed on the semiconductor pattern and facing the source electrode; and a pixel electrode connected to the drain electrode, wherein the drain electrode comprises a bar-shaped portion disposed on the semiconductor pattern and extending in one direction, a compensation portion connected to one distal end portion of the bar-shaped portion, a connecting portion connected to the other distal end portion of the bar-shaped portion, and an pad portion connected to the connecting portion and overlapping the pixel electrode, wherein the bar-shaped portion has a first width and at least portions of the compensation portion and the connecting portion have a second width that is greater than the first width.