TFT Dual Gate Insulator for OLED Aperture Ratio
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Solution Overview
Problem
In organic light emitting displays, the large surface area of capacitors required for high capacity leads to a decrease in the aperture ratio, as the capacitor's surface area needs to increase to enhance its capacity, thereby reducing the display's efficiency.
Innovation Solution
The method involves partially decreasing the thickness of the gate insulating layer using a dual gate insulating layer structure in the TFT, which reduces the capacitor's surface area without altering its capacitance, thereby increasing the aperture ratio of the OLED display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitor's surface area is increased to enhance its capacity, then the capacitance is improved, but the aperture ratio decreases
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by forming multiple gate insulating layers (first gate insulating layer 130, second gate insulating layer 132) and corresponding electrodes (first electrode 124, second electrode 136) in vertical stacking. This dimensional change increases capacitance without increasing the horizontal surface area occupied by the capacitor, thereby resolving the contradiction between capacitance enhancement and aperture ratio maintenance.
Solution Approach 2:
The patent implements a nested structure where the first gate insulating layer 130 and first electrode 124 are positioned within the same horizontal footprint as the second gate insulating layer 132 and second electrode 136. The capacitors are nested vertically one above the other, allowing multiple capacitive elements to occupy the same planar space, thus increasing total capacitance while minimizing surface area occupation and preserving aperture ratio.
2Ease of manufacture
If a conventional single gate insulating layer structure is used, then the manufacturing process is simple, but the capacitor surface area must be large to achieve high capacity
Solution Approach 1:
The patent segments the gate insulating layer into multiple distinct layers: a first gate insulating layer 130 and a second gate insulating layer 132, each with specific thickness ranges (first layer: 400-1000 Å, second layer: 200-800 Å). This segmentation allows the capacitor to achieve higher capacitance through vertical stacking while maintaining a systematic, step-by-step manufacturing process that builds upon conventional single-layer formation techniques, thus balancing manufacturing simplicity with reduced surface area requirements.
Data Source
AI summary
A thin film transistor including a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.