TFT eDRAM With Shallow Bitline for Low-Leakage Scaling
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Solution Overview
Problem
The challenge in developing embedded dynamic random-access memory (eDRAM) is the leakage of selector transistors, which complicates scaling in advanced technology nodes, and the integration of capacitors in lower metal layers due to aggressive pitch scaling, leading to increased complexity in achieving sufficient capacitance and footprint reduction.
Innovation Solution
The use of thin-film transistors (TFTs) as selector transistors in the back end of line (BEOL) layers, with a bottom gate design, reduces leakage and allows for capacitors to be placed in upper metal layers, enabling lower capacitance and aspect ratios while maintaining data retention, and relocating peripheral circuits beneath the memory array to minimize footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used as selector transistors in eDRAM, then data retention can be achieved, but leakage increases and scaling becomes complicated in advanced technology nodes
Solution Approach 1:
The patent changes the material parameter of the selector transistor from conventional silicon-based transistors to oxide semiconductor thin-film transistors (TFTs). This material parameter change fundamentally alters the electrical characteristics, achieving extremely low leakage current while maintaining sufficient on-current for reliable data retention, thus resolving the contradiction between reliability and energy loss.
2Reliability
If capacitors are placed in lower metal layers to achieve sufficient capacitance, then data retention is improved, but pitch scaling becomes aggressive and integration complexity increases
Solution Approach 1:
The patent moves the capacitor placement from lower metal layers to upper metal layers (e.g., M6 or M7 layers). This dimensional relocation in the vertical stack allows capacitors to be positioned where larger metal pitches and thicker inter-layer dielectric layers exist, reducing integration complexity while maintaining sufficient capacitance for data retention through increased capacitor area.
Solution Approach 2:
The patent implements a nested vertical stacking architecture where TFT-based memory cells are formed in upper metal layers (M5-M7), capacitors are placed in the highest metal layers, and peripheral circuits are positioned in lower metal layers (M1-M4). This nested arrangement allows all components to coexist in a compact three-dimensional structure, reducing overall footprint and integration complexity.
3Area of moving object
If eDRAM is scaled to increase density, then area is reduced, but leakage from selector transistors increases and complicates scaling
Solution Approach 1:
The patent changes the selector transistor material to oxide semiconductor TFTs, which inherently provide extremely low leakage current even at scaled dimensions. This material parameter change enables aggressive scaling to increase memory density while maintaining low leakage performance, as the TFT's off-state current remains negligible regardless of device size reduction.
Solution Approach 2:
The patent transitions to a vertical stacking architecture where memory cells are formed in upper metal layers rather than planar integration in lower layers. This vertical dimensionality change allows higher density by utilizing the third dimension (layer stacking), achieving increased memory capacity per unit area without the leakage penalties that plague conventional planar scaling.
4Reliability
If capacitors are designed with higher capacitance to compensate for leakage, then data retention is improved, but capacitor footprint increases
Solution Approach 1:
The patent changes the dielectric material parameter of the capacitor from conventional dielectrics to high-k dielectric materials. This material parameter change increases the capacitance density (capacitance per unit area), allowing sufficient total capacitance for data retention to be achieved with smaller capacitor footprints, thus resolving the contradiction between reliability and area.
Data Source
AI summary
Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.