Thin-Film Transistor Electrode Layout for Fewer Mask Steps
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Solution Overview
Problem
The manufacturing of thin film transistors for transistor array substrates is hindered by the increasing number of mask processes, leading to higher costs and decreased yield, which in turn affects the reliability and uniformity of current characteristics due to increased process errors and etchant influence.
Innovation Solution
A thin film transistor design with a gate electrode and first electrode disposed on the gate insulating layer, where the electrodes intersect the gate insulating layer at acute or obtuse angles, reducing the etchant's influence and process errors by increasing the corner length where the gate insulating layer and electrodes contact, thus minimizing the number of mask processes required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of mask processes is increased to provide all components of the thin film transistor, then manufacturing precision and reliability are improved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The gate electrode and first electrode are formed in the same mask process step, merging two previously separate processes into one. This reduces the total number of mask processes from multiple steps to fewer steps, thereby improving manufacturing yield while maintaining component precision through the integrated formation approach
2Productivity
If the number of mask processes is decreased to improve productivity, then manufacturing cost decreases and yield improves, but process error increases and reliability deteriorates
Solution Approach 1:
The first electrode is designed with an oblique intersection geometry relative to the gate insulating layer edge, creating a locally optimized structure. This oblique configuration reduces etchant influence and process error at the critical interface region, maintaining reliability and current characteristic uniformity even when the total number of mask processes is reduced
3Ease of manufacture
If traditional orthogonal electrode configuration is used, then manufacturing is simpler, but etchant influence and process error increase
Solution Approach 1:
The first electrode is configured to obliquely intersect the gate insulating layer edge rather than forming a perpendicular or orthogonal connection. This asymmetric geometry creates a longer contact length between the electrode and gate insulating layer, which reduces etchant penetration and minimizes process error, thereby improving conductive area precision while maintaining ease of manufacture
Data Source
AI summary
There is provided a thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate and including a channel area, a first conductive area connected to one side of the channel area, and a second conductive area connected to the other side of the channel area; a gate insulating layer covering areas other than the first conductive area and the second conductive area in the semiconductor layer; a gate electrode disposed on the gate insulating layer and overlapping the channel area in a plan view; and a first electrode disposed on the gate insulating layer on the one side of the channel area and in contact with a portion of the first conductive area. A first edge of the first electrode facing the gate electrode obliquely intersects a first edge of the gate insulating layer in a plan view.