TFT Array Substrate Electrode Stacking for High PPI
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Solution Overview
Problem
Increasing the Pixel units per Inch (PPI) in thin film transistor liquid crystal displays (TFT-LCD) typically results in a decrease of the aperture ratio and product yield ratio, making it challenging to enhance display performance without compromising these critical parameters.
Innovation Solution
A thin film transistor array substrate design featuring a glass substrate with scan lines, data lines, and pixel units, where the source electrode is in the same layer as the data lines, and the drain electrode is in a different layer, allowing for larger electrode sizes and maintaining the aperture and yield ratios, even when reducing the distance between adjacent data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between adjacent data lines is reduced to increase PPI, then the pixel density is improved, but the aperture ratio and product yield ratio decrease
Solution Approach 1:
The patent applies three-dimensional stacking by placing the source electrode and drain electrode in different layers (first and second electrode layers respectively), utilizing the vertical dimension to resolve the spatial conflict between electrode size and pixel density. This allows larger electrode areas to be maintained even when pixel dimensions are reduced.
Solution Approach 2:
The patent implements nested layering where the first electrode layer containing the source electrode is positioned between the second electrode layer containing the drain electrode and the active layer. This nested structure allows electrodes to be embedded within the pixel unit volume without increasing the planar footprint, thereby maintaining aperture ratio while enabling higher PPI.
2Quantity of substance
If the distance between adjacent data lines is reduced to increase PPI, then the pixel density is improved, but the product yield ratio decreases
Solution Approach 1:
By transitioning from planar to three-dimensional electrode arrangement with source and drain electrodes in separate layers, the patent maintains adequate electrode dimensions and spacing even at higher PPI. This preserves manufacturing tolerances and reduces defects, thereby maintaining product yield ratio while increasing pixel density.
Solution Approach 2:
The nested layering structure with the first electrode layer positioned between the second electrode layer and active layer allows for robust electrode design that is less sensitive to manufacturing variations. This improves process yield by maintaining reliable electrical connections even when feature sizes are reduced for higher PPI.
3Area of moving object
If the electrode size is increased to maintain aperture ratio, then the aperture ratio is preserved, but the PPI decreases
Solution Approach 1:
The patent resolves this contradiction by extending electrode volume into the third dimension through multi-layer stacking. The source electrode in the first layer and drain electrode in the second layer provide sufficient total electrode area for maintaining aperture ratio while the vertical arrangement reduces the planar footprint, enabling higher PPI.
Solution Approach 2:
By nesting the first electrode layer containing larger source electrodes within the pixel structure and positioning it between the drain electrode layer and active layer, the patent achieves both large electrode areas for high aperture ratio and compact planar dimensions for high PPI.
Data Source
AI summary
A thin film transistor array substrate and a display apparatus are disclosed. The thin film transistor array substrate includes a number of scan lines, data lines and pixel units. Each of the pixel units includes a thin film transistor and a pixel electrode. The thin film transistor includes a gate electrode, a source electrode and a drain electrode. The gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, and the drain electrode is electrically connected to the pixel electrode. The source electrode is arranged in a same layer as the data lines while the drain electrode and the source electrode are respectively arranged in different layers. Therefore, the implementation of the present disclosure may augment the PPI (Pixel units per Inch) of display apparatus without reducing its aperture ratio and product yield ratio.