TFT Source Drain Electrode Tunneling Layer Design
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Solution Overview
Problem
The conventional bottom gate TFT structure for larger TFT-LCD panels faces issues such as increased signal retardation, cross-talk, and non-uniform brightness due to higher resistance in longer gate and data lines, along with etching problems and increased costs from using multiple metal layers like Al and Mo, which decreases productivity and raises material costs.
Innovation Solution
The solution involves modifying the source and drain electrodes by using a single layer of Al alloy with a thin SiNx or SiOxNy tunneling layer between the active layer and electrodes, eliminating the need for multiple metal layers and reducing etching issues, while maintaining low electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple metal layers (Al and Mo) are used for source and drain electrodes, then contact resistance is reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the Mo buffer layer from the electrode structure, retaining only the Al alloy layer. This simplifies the multi-layer structure to a single layer while maintaining low contact resistance through proper material selection and interface engineering with the semiconductor layer
Solution Approach 2:
The patent changes the material parameters by using Al alloy instead of pure Al, and optimizes the thickness and composition parameters to achieve low contact resistance without requiring additional Mo layers, thus simplifying the structure while maintaining electrical performance
2Reliability
If multiple metal layers are deposited, then contact quality improves, but productivity decreases
Solution Approach 1:
By removing the Mo buffer layer deposition step from the manufacturing process, the patent reduces the number of deposition cycles required, thereby increasing manufacturing efficiency and productivity while maintaining contact quality through the optimized Al alloy layer
Solution Approach 2:
The patent combines the functions of the Mo buffer layer and Al layer into a single Al alloy layer that directly contacts the semiconductor, eliminating the need for sequential deposition of multiple layers and streamlining the manufacturing process
3Reliability
If multiple metal layers are used, then contact resistance is reduced, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the Mo layer from the electrode structure, reducing material costs since Mo is more expensive than Al. The single Al alloy layer maintains low contact resistance while significantly reducing manufacturing material costs
Solution Approach 2:
The patent replaces the expensive Mo material with cheaper Al alloy material for the electrode layer that directly contacts the semiconductor, achieving cost reduction while maintaining functional performance through proper material selection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances productivity, reduces production costs, and improves the reliability of the TFT-LCD panels by simplifying the manufacturing process and reducing material expenses, while maintaining low electrical resistance and resolving etching problems.
Implementation Method 1
a thin film of SiNx or SiOxNy through which electrons are allowed to tunnel is provided between the active layer and the source and drain electrodes
Implementation Method 2
A metal thin film is deposited on a substrate (e.g., a glass or a single crystal silicon wafer) by magnetic sputtering
Implementation Method 3
A SiNx or SiOxNy thin film layer is prepared by chemical vapor deposition (CVD) as a gate insulating layer. The semiconductor layer (e.g., an a-Si layer) and the doped semiconductor layer (e.g., an N+ a-Si layer) are deposited in a same process on the gate insulating layer by CVD
Data Source
AI summary
A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source and drain electrodes overlap a source region and a drain region of the active layer, respectively, and a thin film of SiNx or SiOxNy through which electrons are allowed to tunnel is provided between the active layer and the source and drain electrodes.