TFT ESD Protection Circuit Layout for Display Signal Lines
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Solution Overview
Problem
Existing ESD protection circuits in display devices have limited ESD-damage-prevention performance due to the perpendicular orientation of Thin Film Transistors (TFTs) relative to data or gate lines, which restricts the channel length and width-to-length ratio, thereby limiting the effectiveness of electrostatic discharge protection.
Innovation Solution
The ESD protection circuit incorporates TFTs with a channel length direction parallel to the extension direction of the signal lines, featuring a width-to-length ratio less than 0.2, and includes a configuration of first and second TFTs connected to discharge lines that are short-circuited, allowing for improved layout and increased channel length, thereby enhancing ESD-damage-prevention performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TFT channel direction is perpendicular to the data line or gate line extension direction, then the layout is simplified, but the channel length is limited and the width-to-length ratio cannot be reduced sufficiently, resulting in limited ESD-damage-prevention performance
Solution Approach 1:
The patent inverts the conventional TFT orientation by placing the channel length direction parallel to the data line or gate line extension direction, rather than perpendicular. This inversion allows the channel to extend along the signal line direction, achieving a longer channel length and smaller width-to-length ratio, thereby improving ESD protection performance without significantly increasing layout complexity
Solution Approach 2:
The patent utilizes the spatial dimension along the signal line extension direction to accommodate the TFT channel, transforming the layout from a perpendicular orientation to a parallel orientation. This dimensional reconfiguration enables the channel to achieve greater length while maintaining compatibility with the existing pixel electrode and signal line geometry
2Reliability
If the TFT channel length is increased to improve ESD protection, then the ESD-damage-prevention performance is enhanced, but the available space for disposing the TFT is limited
Solution Approach 1:
The patent employs asymmetric TFT configuration where the channel length is extended significantly while the channel width is reduced, creating an asymmetric width-to-length ratio less than 0.2. This asymmetric design allows the TFT to achieve superior ESD protection performance within the limited pixel area by optimizing the dimensional proportions rather than requiring uniform expansion in all directions
3Reliability
If the width-to-length ratio of the TFT channel is reduced to enhance ESD protection, then the ESD-damage-prevention performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent systematically optimizes the TFT channel parameters by reducing the width-to-length ratio to less than 0.2, representing a significant parameter change from conventional designs. This parameter optimization is achieved through coordinated adjustments of both channel width and length dimensions, allowing the TFT to achieve enhanced ESD protection while maintaining manufacturability through controlled parameter variations
Data Source
AI summary
An Electro-Static Discharge (ESD) protection circuit including a Thin Film Transistor (TFT) arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.