TFT ESD Protection Layout for Display Signal Lines
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Solution Overview
Problem
Existing ESD protection circuits in display devices face limitations due to a narrow width-to-length ratio of Thin Film Transistors (TFTs) perpendicular to data or gate lines, restricting their ESD-damage-prevention performance.
Innovation Solution
The ESD protection circuit design includes TFTs with channels parallel to the extension direction of signal lines, allowing for a reduced width-to-length ratio and improved ESD-damage-prevention performance by increasing channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel direction of TFT is perpendicular to data line or gate line extension direction, then the TFT can be disposed in limited space, but the channel length is limited and ESD-damage-prevention performance is limited
Solution Approach 1:
The patent inverts the conventional channel orientation by making it parallel to the data line or gate line extension direction instead of perpendicular. This inversion allows the channel length to extend along the line direction, achieving a smaller width-to-length ratio and improved ESD protection performance without increasing the area occupied by the TFT.
Solution Approach 2:
The patent changes the geometric parameters of the TFT by adjusting the channel width and length relationship. By orienting the channel parallel to the data line or gate line, the effective channel length increases while the channel width decreases, resulting in an optimized width-to-length ratio that enhances ESD damage prevention capability.
2Reliability
If the channel direction of TFT is perpendicular to data line or gate line extension direction, then the TFT can be disposed in limited space, but the width-to-length ratio is limited
Solution Approach 1:
The patent inverts the conventional channel orientation by making it parallel to the data line or gate line extension direction instead of perpendicular. This inversion allows the channel length to extend along the line direction, achieving a smaller width-to-length ratio and improved ESD protection performance without increasing the area occupied by the TFT.
Solution Approach 2:
The patent changes the geometric parameters of the TFT by adjusting the channel width and length relationship. By orienting the channel parallel to the data line or gate line, the effective channel length increases while the channel width decreases, resulting in an optimized width-to-length ratio that enhances ESD damage prevention capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ESD-damage-prevention performance by optimizing the layout and connection of TFTs, reducing space occupation and improving protection against electrostatic damage.
Implementation Method 1
electro-static discharge protection circuit
Data Source
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AI summary
An ESD protection circuit including a TFT arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.