Thin Film Transistor Etch Stop Layer and Laser Crystallization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing thin film transistors (TFTs) face challenges in increasing grain size in the channel region, protecting the semiconductor layer during etching, and reducing production costs, particularly due to the use of excimer lasers which are costly and difficult to manage uniformly.
Innovation Solution
A method involving the formation of an etch stop layer pattern and crystallization of an amorphous silicon layer using a continuous-wave solid-state laser, which enhances grain size and reduces processing costs by optimizing the etch stop layer thickness and laser irradiation parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor layer is made thicker to protect the channel region during etching, then the protection effect is improved, but production cost increases and gate leakage occurs
Solution Approach 1:
An etch stop layer pattern is introduced as an intermediary protective layer between the etching process and the semiconductor layer. This patterned layer provides targeted protection to the channel region during etching, eliminating the need to increase the overall semiconductor layer thickness, thereby avoiding gate leakage and reducing production costs.
2Reliability
If the etch stop layer pattern is formed after the semiconductor layer pattern, then the protection function is achieved, but the number of masking processes increases
Solution Approach 1:
The formation of the etch stop layer pattern and the semiconductor layer pattern are merged into a single masking process. By forming both patterns simultaneously using one mask, the number of masking processes is reduced while still achieving the protective function in the channel region.
3Manufacturing precision
If excimer laser is used for crystallization, then crystallization can be achieved, but equipment management difficulty increases and cost increases
Solution Approach 1:
The patent replaces expensive excimer laser equipment with a more economical continuous-wave solid-state laser. This substitution reduces equipment management complexity and operational costs while still achieving the necessary crystallization of the semiconductor layer for device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases grain size in the channel region, protects the semiconductor layer during etching, and reduces processing costs by using a continuous-wave solid-state laser for crystallization, resulting in improved TFT performance and cost efficiency.
Implementation Method 1
irradiating a laser on the entire surface of the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer
Implementation Method 2
crystallize the amorphous silicon layer into a polycrystalline silicon layer
Implementation Method 3
an etch stop layer pattern disposed on the channel region of the semiconductor layer pattern and having a thickness of 20 to 60 nm
Data Source
AI summary
A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same, which allow a size of a grain of a channel region to be increased, can effectively protect the channel region of a semiconductor layer at the time of etching process, and can reduce processing cost. The thin film transistor includes a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer pattern disposed on the gate insulating layer and including a channel region, a source region and a drain region, an etch stop layer pattern disposed on the channel region of the semiconductor layer pattern and having a thickness of 20 to 60 nm, and source and drain electrodes disposed on the source and drain regions of the semiconductor layer pattern, respectively.