Thin-Film Transistor Etching Block Layer Integration
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Solution Overview
Problem
Conventional thin-film transistor (TFT) technologies face challenges in protecting the semiconductor layer during the etching process, which affects production efficiency and performance, and require additional space for the etching block layer, limiting design flexibility.
Innovation Solution
A new TFT structure comprising a substrate, gate, gate insulating layer, semiconductor oxide layer, source/drain layer, passivation layer, and transparent conducting layer, where the etching block layer is formed after etching the source/drain layer and is integrated into the interface, reducing its thickness and allowing for better protection and insulation of the semiconductor layer, and the semiconductor oxide layer is activated to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching block layer is arranged on the semiconductor layer to protect it during etching, then the semiconductor layer is protected from being destroyed, but the device complexity increases and production efficiency decreases due to the additional fabrication process
Solution Approach 1:
The patent combines the etching block layer with the source/drain layer into a single integrated structure. The source/drain layer serves dual functions: as the conductive source/drain electrode and as the etching protection layer. This merging eliminates the need for a separate etching block layer fabrication process, reducing device complexity while maintaining protection of the semiconductor layer during etching.
Solution Approach 2:
The source/drain layer is designed to perform multiple functions simultaneously: it acts as the conductive path for charge carriers (source/drain function) and as the protection layer during the etching process (etching block function). This multi-functionality reduces the total number of layers and fabrication steps while ensuring both electrical functionality and process protection.
2Reliability
If an etching block layer is added to protect the semiconductor layer, then the semiconductor layer is protected, but the TFT size expands and designing space reduces
Solution Approach 1:
By merging the etching block layer with the source/drain layer, the patent eliminates the need for additional lateral extension beyond the source/drain contact regions. The protection function is achieved within the existing source/drain footprint, preventing any increase in TFT overall size while maintaining adequate protection of the semiconductor layer during etching.
3Productivity
If the semiconductor layer is directly exposed during etching, then production efficiency is maintained, but the semiconductor layer is easily destroyed by strong acid and mixtures
Solution Approach 1:
The source/drain layer serves as both the functional conductive element and the protection layer during etching. This eliminates the need for separate protection layer deposition and removal steps, maintaining production efficiency while ensuring the semiconductor layer is protected from damage by strong acids and etching mixtures throughout the manufacturing process.
4Reliability
If the etching block layer is made thicker to improve protection, then the semiconductor layer is better protected, but the device complexity increases and manufacturing precision requirements increase
Solution Approach 1:
By integrating the etching block function into the source/drain layer, the patent inherits the thickness control benefits already established for the source/drain layer. The source/drain layer thickness is optimized for electrical performance, and this same thickness provides adequate etching protection without requiring additional thickness control specifications, thereby maintaining manufacturing precision while ensuring reliable protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall size of the TFT, improves insulation, and enhances the semiconductor layer's resistance to water, oxygen, and energy, maintaining performance while increasing design space and production efficiency.
Implementation Method 1
The semiconductor oxide layer and the etching block layer are heated for activation and then form a semiconductor layer and an insulating layer, respectively
Data Source
AI summary
A TFT includes a substrate, a gate, a gate insulating layer, a semiconductor oxide layer, a source/drain layer, a passivation layer, and a transparent conducting layer arranged from bottom to top. An etching block layer is formed after the source/drain layer arranged on the semiconductor oxide layer is etched. A method for forming for the TFT includes: depositing and photo-etching a gate on a substrate; depositing a gate insulating layer on the gate; depositing and photo-etching a semiconductor oxide layer on the gate insulating layer; depositing and photo-etching a source/drain layer on the semiconductor oxide layer; etching the source/drain layer on the semiconductor oxide layer for forming an etching block layer; depositing a passivation layer on the source/drain layer and the semiconductor oxide layer; depositing a transparent conducting layer on the passivation layer.