Thin Film Transistor Etching Stop Layer Removal
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Solution Overview
Problem
Conventional thin film transistor manufacturing processes are complicated due to the need for additional photoresist processes in patterning the etching stop layer, which increases complexity and potential damage to the semiconductor layer during the preparation of source and drain electrodes.
Innovation Solution
The manufacturing method involves depositing an etching stop layer with specific through holes on the semiconductor layer, followed by a passivation layer with corresponding through holes, allowing for the exposure and connection of source and drain electrodes without the need for a metal mask, simplifying the process and reducing damage to the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching stop layer is deposited and patterned using conventional photomask methods, then the etching stop layer can prevent etchant from damaging the active layer, but the manufacturing process becomes more complicated due to additional photoresist processes
Solution Approach 1:
The patent extracts and removes the etching stop layer pattern formation step from the conventional manufacturing process. Instead of depositing and patterning a separate etching stop layer using photomasks, the invention directly forms source and drain electrode patterns on the semiconductor layer, eliminating the need for the etching stop layer and its associated photoresist processes while still protecting the semiconductor layer during etching through the electrode pattern itself
Solution Approach 2:
The source and drain electrode patterns serve dual functions: they are both the final functional electrodes and the protective masks during the etching process. The electrodes themselves provide the protection that would otherwise require a separate etching stop layer, making the process self-service and eliminating redundant steps
2Manufacturing precision
If additional photoresist processes are used for patterning the etching stop layer, then the etching stop layer can be precisely formed, but the manufacturing process time increases
Solution Approach 1:
The invention removes the multi-step photoresist patterning process for the etching stop layer entirely. By directly forming electrode patterns without a separate etching stop layer, the process eliminates deposition, photomask alignment, photoresist coating, exposure, development, and etching stop layer removal steps, significantly reducing manufacturing time while maintaining precision through direct electrode pattern formation
Solution Approach 2:
The invention merges the etching stop layer function with the source and drain electrode formation into a single integrated process. The electrode patterns are formed directly in the positions where the etching stop layer would have been, combining multiple functions (etch protection and electrode formation) into one step, thereby reducing both time and process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the thin film transistor manufacturing process by eliminating the need for a metal mask in patterning the etching stop layer, thereby reducing process complexity and minimizing damage to the semiconductor layer during electrode preparation.
Implementation Method 1
The etching stop layer can prevent the etchant to etch the active layer in the subsequent preparation of the source and the drain of the thin film transistor
Implementation Method 2
a passivation layer covered the etching stop layer
Data Source
AI summary
The present invention discloses a thin film transistor, a liquid crystal display and the manufacturing method of a thin film transistor. The thin film transistor includes a substrate, a gate electrode formed on the surface of the substrate; a gate insulting layer covered on the gate electrode; a semiconductor layer disposed on the surface of the gate insulating layer and corresponding to the gate electrode; an etching stop layer covered the semiconductor layer and having a first through hole and a second through hole; a passivation layer covered the etching stop layer having a third through hole and a fourth through hole; a source electrode disposed on the passivation layer and connected to the semiconductor layer via the first and the third through hole; and a drain electrode disposed on the passivation layer and connected to the semiconductor layer via the second and the fourth through hole.