TFT Manufacturing Etching Process Undercut Prevention
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Solution Overview
Problem
The existing method for manufacturing thin film transistors (TFTs) using a combination of wet and dry etching steps often results in an undercut between the semiconductor and doped semiconductor layers, which can lead to manufacturing inefficiencies and yield issues.
Innovation Solution
A method involving four etching steps, including sequential formation of source/drain electrode, doped semiconductor, and semiconductor layers, with specific etching processes and ashing treatments to prevent undercuts, utilizing a gradient angle approach for the source/drain electrode to reduce breakage risks during subsequent film deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one wet etching step and one dry etching step are used to form source/drain electrode and semiconductor layers, then the manufacturing process is simplified, but an undercut occurs between the semiconductor layer and doped semiconductor layer
Solution Approach 1:
The patent divides the etching process into four distinct steps: first wet etching for source/drain electrode, first dry etching for semiconductor layer, second wet etching for doped semiconductor layer, and second dry etching for refinement. This segmentation allows each etching step to be optimized independently, preventing undercut formation while maintaining reasonable process complexity.
Solution Approach 2:
The patent performs preliminary actions by forming the source/drain electrode pattern first, then using it as a mask for subsequent semiconductor layer etching. The doped semiconductor layer is then formed with controlled etching that stops before reaching the source/drain electrode, creating a preliminary structure that prevents undercut in final alignment.
2Manufacturing precision
If photoresist is used for patterning during etching, then the pattern can be formed accurately, but the photoresist may crack or break during subsequent film deposition
Solution Approach 1:
The patent performs preliminary hard-baking of the photoresist layer before subsequent film deposition steps. This hard-baking strengthens the photoresist structure, making it resistant to cracking or breaking during the deposition process while maintaining its patterning accuracy.
Solution Approach 2:
The patent applies a cushioning effect by performing hard-baking to pre-strengthen the photoresist layer, creating a buffer against the mechanical stresses that will occur during subsequent high-temperature film deposition processes, thereby preventing photoresist failure.
3Ease of manufacture
If the source/drain electrode has a vertical profile, then the etching is simpler, but the subsequent film deposition may cause breakage at the sharp corners
Solution Approach 1:
The patent modifies the source/drain electrode profile from a vertical sharp-cornered structure to a rounded or curved profile through controlled etching parameters. This curvature eliminates sharp corners that would concentrate stress during film deposition, preventing breakage while adding only minimal complexity to the etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents undercuts between semiconductor and doped semiconductor layers, improving manufacturing efficiency and reducing the risk of photoresist cracking and breakage, thereby enhancing the quality and yield of TFTs.
Implementation Method 1
performing ashing treatment on the photoresist layer so as to remove the photoresist layer on the channel region
Implementation Method 2
hard-baking the photoresist layer after the ashing treatment
Implementation Method 3
wet etching a source/drain metal layer using a diluted etchant
Implementation Method 4
dry etching the pattern of semiconductor layer and the pattern of doped semiconductor layer
Data Source
AI summary
The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer.