TFT Floating Gate Memory Cell Vertical Stacking
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Solution Overview
Problem
Conventional techniques for reducing memory cell size in semiconductor devices face challenges in scaling down memory cell size without reducing memory capacitance per unit area, leading to inadequate high-density memory development.
Innovation Solution
A method for creating a thin-film transistor (TFT) floating gate memory cell structure with a three-dimensional array, utilizing a substrate with N+ polysilicon source or drain regions, a P− polysilicon channel layer, a silicon floating gate sandwiched by oxide layers, and a control gate, allowing for high-density memory storage with low thermal budget and compatibility with CMOS process technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional techniques are used to reduce memory cell size, then device geometry is reduced, but memory capacitance per unit area is also reduced
Solution Approach 1:
The patent transitions from planar memory cell structures to three-dimensional vertically-stacked structures. Multiple memory cells are stacked vertically above a common substrate area, utilizing the vertical dimension to increase storage density without reducing the lateral footprint. This allows maintaining memory capacitance per unit area while achieving smaller effective cell size through vertical stacking.
Solution Approach 2:
The patent implements nested structures where control gates, floating gates, and insulating layers are stacked vertically within a compact footprint. Each memory cell layer is nested above others, with shared substrate regions supporting multiple stacked cells, effectively nesting multiple functional elements within a small lateral area while preserving capacitance.
2Productivity
If device geometry is reduced to increase circuit density, then more devices fit on a wafer, but fabrication process limits are reached
Solution Approach 1:
By moving to three-dimensional vertically-stacked memory structures, the patent achieves higher circuit density without further reducing lateral feature sizes to the point where fabrication processes become infeasible. The vertical stacking allows density improvement through the Z-dimension while maintaining manufacturable lateral dimensions.
3Length of moving object
If memory cell size is reduced without maintaining capacitance, then high-density memory development is enabled, but reliability is compromised
Solution Approach 1:
The patent employs nested vertically-stacked structures where multiple memory cells share common substrate regions and support circuits. Each stacked cell maintains adequate capacitance through its floating gate and control gate configuration, while the overall cell footprint is reduced via vertical integration, preserving reliability despite smaller lateral dimensions.
Solution Approach 2:
The patent uses composite material structures including silicon-oxide-nitride-oxide-silicon (SONOS) stacks, polysilicon control gates, and carefully engineered insulating layers. These composite structures ensure adequate capacitance and charge retention reliability while enabling compact vertical stacking to reduce effective cell size.
Data Source
AI summary
A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.