TFT Array Substrate Gate Driving Circuit for 2D-3D Mode Switching
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Solution Overview
Problem
Conventional 3D display devices face inconvenience in converting between 3D and 2D display modes due to the need for specialized image processing systems to handle different image data signals for each mode, making mutual conversion cumbersome.
Innovation Solution
A TFT array substrate design with multiple gate lines, gate driving circuits, and clock signal lines, where transistors and shift registers are configured to control signal flow and reset processes, allowing for easy switching between 2D and 3D display modes by controlling transistor states via control lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If specialized image processing systems are used to handle different image data signals for 3D and 2D modes, then display mode functionality is improved, but device complexity and ease of operation deteriorate due to cumbersome conversion requirements
Solution Approach 1:
The gate driving circuit is designed to perform multiple functions by processing both 2D and 3D image data signals through the same circuit path. The circuit can operate in different modes (2D, 3D, and intermediate states) by controlling the timing and synchronization of clock signals, eliminating the need for separate specialized processing systems for each display mode.
Solution Approach 2:
The circuit employs dynamic clock signal control where the timing and phase of clock signals can be adjusted to switch between 2D and 3D modes. By dynamically changing the synchronization relationship between first and second clock signals, the circuit adapts its operation to handle different image data signals without requiring physical reconfiguration or complex mode conversion operations.
2Productivity
If separate clock signal lines are used for first and second shift registers, then signal processing capability is improved, but device complexity increases
Solution Approach 1:
The clock signal system is segmented into first and second clock signal lines, each dedicated to driving the first and second shift registers respectively. This segmentation allows independent control and timing adjustment of each shift register, enabling the circuit to process different image data signals simultaneously or in sequence, thereby improving signal processing capability while maintaining clear signal paths.
Solution Approach 2:
Despite the segmentation, the clock signal generation is merged at the source through a single control mechanism that generates both first and second clock signals. The clock signal lines share common control logic and can be synchronized or desynchronized as needed, combining the benefits of separate signal paths with the simplicity of unified control, thus avoiding excessive circuit complexity.
Data Source
AI summary
A TFT array substrate is disclosed. The array substrate includes gate lines, first and second gate driving circuits, first, second, third, and fourth clock signal lines, first and second initial signal lines, first and second initial transistors, and first, second, third, and fourth clock transistors. The first gate driving circuit includes m stages of first repeating units. The second gate driving circuit includes n stages of second repeating units. Where m and n are positive integers, and 2≦m, 2≦n.