Thin Film Transistor Gate Electrode Inclined Portion Design
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Solution Overview
Problem
The formation of protrusions on the surface of active layers in thin film transistors during crystallization leads to high hot carrier stress, reduced breakdown voltage, and increased vulnerability to electrostatic defects, particularly in top gate type TFTs, and disconnection issues in bottom gate type TFTs due to agglomeration phenomena.
Innovation Solution
A thin film transistor design featuring a gate electrode with a flat portion and an inclined portion having a height-to-width ratio of 1.192 or less, with a polysilicon active layer on a gate insulating layer and source and drain electrodes connected to the active layer, which reduces the gradient of the gate electrode to prevent disconnection and hot carrier stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a typical top gate type TFT is formed with a gate electrode covering protrusions on the active layer, then the gate insulating layer and gate electrode can be formed sequentially, but the protrusions cause high hot carrier stress and reduced breakdown voltage
Solution Approach 1:
The patent inverts the conventional sequence by first forming the gate electrode and gate insulating layer, then forming the active layer on top. This inversion allows the active layer to be formed at a flat interface rather than covering protrusions, eliminating hot carrier stress while maintaining manufacturing feasibility
Solution Approach 2:
The gate electrode and gate insulating layer are formed in advance before the active layer is created. This preliminary action establishes a flat reference surface that prevents protrusion formation during subsequent active layer crystallization, thereby improving reliability
2Loss of energy
If the thickness of the gate insulating layer is reduced to achieve low power consumption and slim design, then power consumption and device thickness are reduced, but protrusions make the TFT more vulnerable to electrostatic defects
Solution Approach 1:
By inverting the formation sequence to create the gate structure first and then forming the active layer on top, the patent eliminates protrusions that would otherwise concentrate electric fields. This allows safe reduction of gate insulating layer thickness without increasing electrostatic defect vulnerability
3Manufacturing precision
If amorphous silicon layer is crystallized using excimer laser to form polysilicon, then the active layer can be formed, but protrusions are formed at locations where grains meet
Solution Approach 1:
The patent inverts the conventional approach by forming the gate structure first and then creating the active layer on top through crystallization. This inversion ensures that grains grow on a flat surface rather than forming protrusions, maintaining both manufacturing precision and surface uniformity
Solution Approach 2:
The patent changes the dimensional relationship by forming the active layer in a new dimension (on top of the gate structure) rather than having it form the base layer. This dimensional reorganization prevents grain boundary protrusions from affecting the interface quality
4Ease of manufacture
If the gate electrode is positioned to cover protrusions, then the gate insulating layer can be formed over the active layer, but the channel is formed at a non-uniform interface causing high hot carrier stress
Solution Approach 1:
The patent inverts the conventional structure by positioning the gate electrode below the active layer rather than above. This inversion creates a uniform interface for channel formation, eliminating the non-uniform contact between gate and active layer that causes hot carrier stress
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents disconnection of the polysilicon layer, reduces hot carrier stress, and enhances the reliability and production yield of thin film transistors by forming a channel at a flat interface, allowing for improved breakdown voltage and reduced manufacturing complexity.
Implementation Method 1
amorphous silicon layer is first formed on a substrate 10, and is crystallized using an excimer laser so as to form polysilicon
Implementation Method 2
a gate insulating layer disposed on the substrate to cover the gate electrode
Data Source
AI summary
A thin film transistor includes a gate electrode on a substrate. The gate electrode includes a flat portion and an inclined portion at a side of the flat portion. A ratio of a height to a width (height/width) of the inclined portion is 1.192 or less. The thin film transistor also includes a gate insulating layer disposed on the substrate to cover the gate electrode and a polysilicon active layer on the gate insulating layer and over the gate electrode. The thin film transistor further includes a source electrode and a drain electrode respectively connected to two opposite end portions of the polysilicon active layer.