Thin Film Transistor Substrate Gate Electrode Inclination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In liquid crystal displays, thin film transistors with high ON-current and reduced size face challenges in maintaining a high aperture ratio and minimizing parasitic capacitance and kickback voltage due to increased width-to-length ratios, which affects display quality.
Innovation Solution
A thin film transistor substrate design with a gate electrode and drain electrode structure where one electrode is spaced apart from the gate electrode, reducing parasitic capacitance and kickback voltage, and optimizing the channel length to maintain high ON-current while minimizing transistor size, achieved through specific layer formations and masking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the width-to-length ratio of the channel is increased to increase ON-current, then the ON-current increases, but the size of the thin film transistor increases, thereby decreasing the aperture ratio
Solution Approach 1:
The source electrode is configured to overlap with the gate electrode in the plan view, utilizing the vertical dimension (z-axis) to create a three-dimensional electrode arrangement. This dimensional change allows the source electrode to be positioned such that it overlaps the gate electrode vertically while being spaced apart horizontally, effectively reducing the parasitic capacitance between source and gate electrodes while maintaining a compact footprint that preserves aperture ratio
2Area of stationary object
If the size of the thin film transistor is reduced, then the aperture ratio improves, but the parasitic capacitance between gate electrode and source electrode increases
Solution Approach 1:
The source electrode is configured to overlap with the gate electrode in the plan view, utilizing the vertical dimension (z-axis) to create a three-dimensional electrode arrangement. This dimensional change allows the source electrode to be positioned such that it overlaps the gate electrode vertically while being spaced apart horizontally, effectively reducing the parasitic capacitance between source and gate electrodes while maintaining a compact footprint that preserves aperture ratio
3Area of stationary object
If the size of the thin film transistor is reduced, then the aperture ratio improves, but the kickback voltage increases
Solution Approach 1:
The source electrode is configured to overlap with the gate electrode in the plan view, utilizing the vertical dimension (z-axis) to create a three-dimensional electrode arrangement. This dimensional change allows the source electrode to be positioned such that it overlaps the gate electrode vertically while being spaced apart horizontally, effectively reducing the parasitic capacitance between source and gate electrodes while maintaining a compact footprint that preserves aperture ratio
Data Source
AI summary
A display apparatus includes a thin film transistor substrate, a substrate facing the thin film transistor substrate, and a liquid crystal layer. The thin film transistor substrate includes an insulating substrate, a gate electrode disposed on a surface of the insulating substrate, a gate insulating layer covering the gate electrode, a semiconductor layer disposed on the gate insulating layer, a source electrode disposed on the semiconductor layer, and a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode. One of the source electrode and the drain electrode is spaced apart from the gate electrode in a plan view. The gate electrode includes a side surface inclined with respect to the surface of the insulating substrate and is partially overlapped with a portion of the source electrode or the drain electrode in a direction perpendicular to the side surface of the gate electrode.