Thin Film Transistor Gate Insulation Concave Region
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Solution Overview
Problem
The existing ion-doping process for LTPS TFTs damages the lattice structure, decreases carrier mobility, and complicates the removal of photoresist masks, leading to asymmetry in threshold voltages between P-type and N-type transistors, which complicates CMOS device driving circuits.
Innovation Solution
A concave region is formed in the gate insulation layer of the thin film transistor, reducing the thickness of the gate insulation layer and thereby decreasing the threshold voltage, eliminating the need for ion-implantation and simplifying the manufacturing process by making the threshold voltage adjustment independent of ion doping concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion-implantation process is performed on channels to change energy band structure and threshold voltages, then threshold voltage asymmetry between P-type and N-type LTPS TFTs is eliminated, but carrier mobility decreases due to lattice structure damage
Solution Approach 1:
The gate insulation layer thickness is locally reduced by forming a concave region only in specific areas (source region, drain region, or channel region) rather than uniformly across the entire gate insulation layer. This localized modification allows threshold voltage adjustment without subjecting the entire active layer to ion-implantation damage, thereby maintaining carrier mobility in undamaged regions while achieving the desired threshold voltage symmetry.
Solution Approach 2:
Instead of using ion-implantation to change the chemical composition and energy band structure of the channel, the invention changes the physical parameter of gate insulation layer thickness. By reducing the thickness locally through concave region formation, the electric field distribution and threshold voltage are modified without introducing lattice damage, thus avoiding the trade-off between threshold voltage control and carrier mobility preservation.
2Reliability
If ion-implantation process is performed on channels, then threshold voltage adjustment is achieved, but manufacturing process complexity increases due to photoresist mask removal difficulties
Solution Approach 1:
The invention extracts the threshold voltage control function from the ion-implantation process and relocates it to the gate insulation layer structure design. By forming concave regions through standard photolithography and etching processes, the need for complex ion-implantation mask removal is eliminated, simplifying the manufacturing process while maintaining precise threshold voltage control capability.
3Use of energy by moving object
If gate insulation layer thickness is reduced by forming concave region, then threshold voltage decreases and power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The concave region is formed locally in specific areas (source region, drain region, or channel region) rather than uniformly across the entire gate insulation layer. This localized approach allows for more relaxed precision requirements compared to uniform thinning, as the threshold voltage adjustment can be achieved through controlled local modifications using standard photolithography and etching techniques, reducing the overall manufacturing precision burden while still achieving power consumption reduction.
Data Source
AI summary
An embodiment of the disclosed technology provides a thin film transistor device comprising a source electrode, a drain electrode, a gate electrode, an active layer corresponding to the gate electrode, and a gate insulation layer formed between the gate electrode and the active layer; a concave region corresponding to the gate electrode is provided in the gate insulation layer.