Thin Film Transistor Gate Insulation Segmentation for Polysilicon Crystallization

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Solution Overview

Problem

The formation of a thin film transistor with a bottom gate structure often results in a height difference in the gate insulating layer, which hinders the crystallization of the semiconductor layer, affecting the transistor's performance.

Innovation Solution

A thin film transistor design that includes a gate on a substrate with a gate insulating layer, supported by first and second support portions on both sides of the gate, which are configured to support a semiconductor layer and reduce the height difference, using conductive materials like aluminum to form a solid solution for ohmic contact, and employing a laser annealing process to convert amorphous silicon into polysilicon.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a bottom gate structure is used in thin film transistor formation, then the device structure is simplified, but a height difference is created in the gate insulating layer that hinders semiconductor layer crystallization

Engineering Contradiction:
Improvedevice structureVSAvoidcrystallization quality
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The gate insulating layer is segmented into a first insulating layer and a second insulating layer. The first insulating layer is formed on the substrate and gate, while the second insulating layer is formed on the first insulating layer. This segmentation allows the gate insulating layer to be formed in multiple steps, enabling better control over the height difference and providing a more favorable surface for semiconductor layer crystallization while maintaining the simplified bottom gate structure.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If the gate insulating layer has a height difference, then the bottom gate structure can be formed, but the semiconductor layer crystallization is hindered

Engineering Contradiction:
Improvebottom gate structure formationVSAvoidtransistor performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate insulating layer is formed preliminarily in a two-layer structure before forming the semiconductor layer. The first insulating layer is formed on the substrate and gate, and the second insulating layer is formed on the first insulating layer. This preliminary formation of a multi-layer gate insulating structure creates a more favorable surface for subsequent semiconductor layer deposition and crystallization, ensuring better transistor performance while maintaining ease of manufacture.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If amorphous silicon is used in the semiconductor layer, then the manufacturing process is simplified, but contact resistance is high and power consumption increases

Engineering Contradiction:
Improvesemiconductor layer formationVSAvoidpower consumption
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The semiconductor layer undergoes a phase change from amorphous silicon to polysilicon through laser annealing treatment. This parameter change in the material structure transforms the semiconductor properties, reducing contact resistance and power consumption while maintaining the manufacturing simplicity of using amorphous silicon as the starting material. The laser annealing process converts the amorphous silicon into a more conductive polysilicon form.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the crystallization effect of the semiconductor layer, enhancing the performance of the thin film transistor by reducing contact resistance and power consumption while simplifying the device structure.

Implementation Method 1

employing a laser annealing process to convert amorphous silicon into polysilicon

Methodology Applied
Scientific EffectLaser annealing: Annealing

Implementation Method 2

employing a laser annealing process to convert amorphous silicon into polysilicon

Methodology Applied
Scientific EffectLaser heating: Laser

Implementation Method 3

a solid solution of a metal and a semiconductor material is formed in areas where the first support portion and the second support portion are in contact with the semiconductor layer respectively

Methodology Applied
Scientific EffectSolid solution formation: Solid Solution Strengthening

Data Source

PatentUS11121257B2Thin film transistor, pixel structure, display device and manufacturing method
Publication Date: 2021.09.14 BOE TECHNOLOGY GROUP CO LTD
  • US11121257B2 patent drawing
  • US11121257B2 patent drawing
  • US11121257B2 patent drawing

AI summary

The present disclosure provides a thin film transistor, a pixel structure, a display device, and a manufacturing method. The thin film transistor includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain respectively connected to the semiconductor layer. The first support portion and the second support portion are respectively configured to support the semiconductor layer.