Thin-Film Transistor Gate Layering for Display s-Factor Tuning
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Solution Overview
Problem
Existing display apparatuses face challenges in optimizing the properties of thin-film transistors, particularly the sub-threshold swing (s-factor) at or below the threshold voltage, which affects the performance of polysilicon and oxide semiconductor transistors, leading to variations in characteristics based on location and transistor type.
Innovation Solution
The display apparatus is designed with differently configured gate electrodes, insulating layers, and source/drain structures for polysilicon and oxide semiconductor transistors, including varying numbers of layers and materials to optimize the s-factor for each transistor type, with specific configurations for switching and driving transistors to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If polysilicon thin-film transistors and oxide semiconductor thin-film transistors are formed on the same substrate with identical structures, then manufacturing complexity is reduced, but transistor performance characteristics cannot be optimized for different locations and functions
Solution Approach 1:
The patent applies local quality by configuring different gate electrode structures for different transistor locations and functions. Specifically, switching transistors have gate electrodes with first, second, and third gate lines, while driving transistors have gate electrodes with first and second gate lines only. This localized structural differentiation optimizes performance characteristics for each transistor type without requiring complete redesign of all transistors.
Solution Approach 2:
The gate electrode structure is segmented into multiple gate lines (first gate line, second gate line, third gate line) that can be independently configured. This segmentation allows different portions of the gate electrode to serve different functions - the third gate line is present in switching transistors for enhanced switching control, while being omitted in driving transistors to simplify the structure where it is not needed.
2Reliability
If the gate electrode structure is differentiated for each transistor type, then transistor performance is optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent employs a dynamic manufacturing approach where the gate electrode structure is formed in stages. The first and second gate lines are formed for all transistors, then the third gate line is selectively formed only for switching transistors based on their specific location and function requirements. This dynamic formation process allows performance optimization while managing manufacturing complexity through selective processing.
Data Source
AI summary
A display apparatus including a first thin-film transistor, a second thin-film transistor and a third thin-film transistor is provided. The first thin-film transistor includes a first active layer composed of a polysilicon material, a first gate electrode overlapping the first active layer such that a first gate insulating layer is interposed therebetween, a first source electrode and a first drain electrode. The first gate electrode includes n layers. The first source electrode and the first drain electrode are connected to the first active layer. The second thin-film transistor includes a second active layer composed of a polysilicon material, a second gate electrode overlapping the second active layer such that a first gate insulating layer is interposed therebetween, a second source electrode and a second drain electrode. The second gate electrode includes n+1 layers. The second source electrode and the second drain electrode are connected to the second active layer.