Thin-Film Transistor Gate Line and Electrode Layering
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Solution Overview
Problem
Conventional thin-film semiconductor devices for display apparatus face challenges in simultaneously achieving low heat conductivity for gate electrodes and low resistivity for gate lines, leading to issues with parasitic capacitance and signal delay, especially with increased panel dimensions.
Innovation Solution
The device features a gate line and gate electrode formed in different layers, allowing for the selection of materials suitable for each component, and eliminates parasitic capacitance by not having the gate line and power supply line cross each other, while improving flatness and flexibility in transistor layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate electrode and gate line are formed in the same layer, then manufacturing process is simplified, but parasitic capacitance increases and material selection is constrained
Solution Approach 1:
The patent divides the gate electrode and gate line into separate layers (gate electrode layer and gate line layer), allowing independent material selection and reducing parasitic capacitance between them. This segmentation resolves the contradiction by sacrificing some manufacturing simplicity to achieve lower parasitic capacitance and greater design flexibility.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by placing the gate line layer above the interlayer insulating film that covers the gate electrode layer. This vertical separation in the third dimension effectively reduces parasitic capacitance while maintaining electrical connection through conductive portions.
2Temperature
If gate electrode material prioritizes low heat conductivity, then laser annealing performance improves, but gate line resistivity increases causing signal delay
Solution Approach 1:
The patent applies different material properties to different components: the gate electrode uses materials with low heat conductivity (such as tungsten or molybdenum) for optimal laser annealing performance, while the gate line uses materials with low resistivity (such as aluminum or copper alloys) for optimal signal transmission. This local differentiation resolves the contradiction by optimizing each component for its specific function.
Solution Approach 2:
The patent employs composite material structures where the gate electrode layer and gate line layer are formed from different materials, each selected for its specific properties. The gate electrode layer may use tungsten or molybdenum for heat management, while the gate line layer uses aluminum or copper for electrical conductivity, creating a composite structure that satisfies both requirements.
3Adaptability or versatility
If gate line and power supply line cross each other, then layout flexibility is maintained, but parasitic capacitance increases
Solution Approach 1:
The patent eliminates crossing between gate line and power supply line by routing them in the same layer (gate line layer) but at different horizontal positions, separated by the interlayer insulating film thickness in the vertical dimension. This three-dimensional arrangement prevents parasitic capacitance while maintaining layout flexibility through proper routing design.
4Area of stationary object
If panel size increases, then display capability improves, but signal delay and parasitic capacitance effects worsen
Solution Approach 1:
The patent optimizes the gate line layer with materials and structures specifically designed for low resistivity and high current carrying capacity to minimize signal delay in large panel applications. This local optimization of the gate line structure compensates for the increased distance and reduced signal integrity issues in larger displays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of thin-film transistors by reducing parasitic capacitance, improving flatness, and increasing the area for semiconductor layers, even with low carrier mobility, thus supporting higher display capabilities.
Implementation Method 1
Laser annealing which uses laser beam for heating has attracted attention as a type of low temperature process. Laser annealing includes locally heating and melting, by irradiating laser beam, non-single crystal semiconductor thin film such as amorphous silicon laminated on an insulating substrate with low heat resistance such as glass, and crystallizing the semiconductor thin film during the cooling process.
Data Source
AI summary
A thin-film semiconductor device for a display apparatus according to the present disclosure includes: a gate electrode above a substrate; a gate insulating film above the gate electrode; a semiconductor layer on the gate insulating film; a first electrode above the semiconductor layer; a second electrode in a same layer as the first electrode; an interlayer insulating film covering the first electrode and the second electrode; a gate line above the interlayer insulating film; and a power supply line in a same layer as the gate line and adjacent to the gate line. Furthermore, the gate electrode and the gate line are electrically connected via a first conductive portion, and the second electrode and the power supply line are electrically connected via a second conductive portion.