TFT Substrate Gate Line IZO Layer Reflectance Reduction
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Solution Overview
Problem
Conventional liquid crystal displays (LCDs) face challenges in minimizing bezel size due to the reflection of gate lines, which affects the contrast ratio and surface reflectance, especially when the TFT array panel is positioned at the top side, leading to increased surface reflectance and deteriorated contrast.
Innovation Solution
Incorporating an indium zinc oxide (IZO) middle layer between the titanium lower layer and copper upper layer in the gate line structure to minimize reflectance, and using a TFT array panel with a triple-layered structure for both gate lines and pixel electrodes, which includes a titanium lower layer, an IZO middle layer, and a copper upper layer, to reduce reflection and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate lines are made visible to reduce manufacturing complexity, then manufacturing process is simplified, but surface reflectance increases and contrast ratio deteriorates
Solution Approach 1:
An IZO (indium zinc oxide) middle layer is introduced between the titanium lower layer and copper upper layer of the gate line structure. This intermediary layer has optimized optical properties that reduce reflectance while maintaining electrical conductivity, thereby resolving the contradiction between manufacturing simplicity and surface reflectance control.
Solution Approach 2:
The gate line is constructed as a composite structure with three distinct layers (titanium, IZO, and copper), each contributing different properties. The titanium layer provides adhesion and barrier properties, the IZO layer optimizes optical characteristics by reducing reflectance, and the copper layer provides low electrical resistance, collectively solving both manufacturing and optical performance requirements.
2Object-affected harmful factors
If gate line reflection is reduced by adding IZO middle layer, then surface reflectance decreases and contrast ratio improves, but manufacturing process complexity increases
Solution Approach 1:
The IZO middle layer serves multiple functions simultaneously: it provides optical optimization by reducing reflectance, maintains electrical conductivity for gate line functionality, and offers adhesion between the titanium and copper layers. This multi-functionality reduces the need for additional separate layers or processes, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The optical and electrical parameters of the gate line are optimized by carefully controlling the thickness and composition of the IZO layer. By adjusting these parameters, the reflectance is minimized while maintaining acceptable electrical performance, achieving a balance between optical improvement and structural complexity.
3Length of stationary object
If TFT array panel is positioned at top side to minimize bezel, then bezel size is reduced, but gate line reflection increases and contrast ratio deteriorates
Solution Approach 1:
The gate line structure is specifically designed to convert the potentially harmful reflection effect into a beneficial low-reflectance surface. The IZO layer's optical properties are optimized to minimize reflection in the viewing direction, thereby allowing the TFT array panel to be positioned at the top side with minimal bezel without suffering from gate line reflection issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IZO middle layer effectively minimizes gate line reflection, allowing for a thinner bezel in LCDs by reducing surface reflectance and enhancing the contrast ratio, while also simplifying the manufacturing process by enabling simultaneous deposition of gate lines and pixel electrodes.
Implementation Method 1
the thickness of the lower layer and the middle layer may be in a range such that light reflected from the lower layer including titanium generates destructive interference with light reflected from the IZO middle layer, thereby minimizing reflection of the gate line
Data Source
AI summary
A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer.