TFT Array Panel Gate Line RC Compensation via Overlapping Capacitance
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Solution Overview
Problem
The existing display panel designs with slits for sensors and cameras result in inconsistent gate line RC values between the slitting-edge and normal display areas, leading to uneven color display.
Innovation Solution
A thin film transistor (TFT) array panel design that includes a first metallic routing layer with a first data line and a second metallic routing layer with a first gate line, where the first data line and gate line form overlapping capacitances through an interlayer dielectric layer to compensate for RC values, ensuring consistency in gate line RC values across the slitting-edge and primary display areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the panel uses a slit design for sensor and camera placement, then the front sensor and camera positions are retained, but the gate line RC value at the slitting edge becomes different from the normal display area, causing color display inconsistency
Solution Approach 1:
The patent applies local quality by introducing a compensation capacitor specifically at the slitting-edge display area. This capacitor is connected to the gate line at the slit edge where the RC value differs, providing localized compensation without affecting other areas. The compensation capacitor has a capacitance value specifically designed to offset the RC difference caused by the slit structure, thereby maintaining uniform threshold voltages and consistent color display across the entire panel including the slit edge region.
2Adaptability or versatility
If the gate line winds at the slitting edge to accommodate the slit design, then the sensor and camera positions are maintained, but the gate line RC value becomes inconsistent with the normal display area, resulting in split display
Solution Approach 1:
The patent applies preliminary anti-action by proactively compensating for the RC value difference before it causes display inconsistency. The compensation capacitor is pre-configured at the gate line at the slitting edge with a capacitance value that anticipates and counteracts the RC difference caused by the slit structure. This preliminary compensation ensures that the threshold voltage remains consistent across the entire panel, preventing display splitting and maintaining reliability.
3Manufacturing precision
If the data line RC value changes gradually in a round slit design, then the difference between slitting-edge and normal display area is reduced, but a gate line RC value compensation structure is still required to achieve complete uniformity
Solution Approach 1:
The patent applies parameter changes by adjusting the capacitance value of the compensation capacitor to precisely match the RC difference at the slitting edge. By carefully selecting the capacitance parameter, the compensation capacitor effectively offsets the RC value difference caused by the slit structure. This parameter-based compensation achieves complete display uniformity with a relatively simple structure, avoiding the need for complex routing modifications while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively compensates for the differences in gate line RC values, resolving the issue of uneven color display on the slitting edge and normal display areas, thereby achieving consistent color representation.
Implementation Method 1
the first data line and gate line form overlapping capacitances through an interlayer dielectric layer to compensate for RC values
Data Source
AI summary
A TFT array panel includes a primary display area and a slitting-edge display area. In the slitting-edge display area, a first metallic routing layer includes a first data line and a second metallic routing layer includes a first gate line. The first data line is connected to the second metallic routing layer through a hole in the interlayer dielectric layer so that the first data line overlaps the first gate line to form an overlapping capacitance to compensate for a gate line RC value.