Thin-Film Transistor Gate Opening Layout for Low Leakage
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Solution Overview
Problem
Poly-silicon thin film transistors (TFTs) suffer from high leakage current due to their orderly lattice arrangement, leading to poor display performance as the pixel units fail to turn off properly, especially at high pixels per inch (PPI) densities where the U-shaped dual-gate structure is not feasible.
Innovation Solution
A thin film transistor design with a gate electrode having an opening, featuring sequentially arranged lightly and heavily doped regions, which reduces the electric field and hot carriers, and includes additional lightly doped regions at the sides of the channel to minimize leakage current without increasing on-state current significantly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If poly-silicon TFT structure is used, then electron mobility and resolution are improved, but leakage current increases
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in specific regions of the active layer. The channel region maintains light doping for high electron mobility, while the source and drain regions use heavy doping to reduce leakage current. This spatial variation in doping quality resolves the contradiction between speed and harmful leakage effects.
Solution Approach 2:
The patent changes the doping concentration parameter from uniform to non-uniform distribution. By adjusting the doping concentration in the source and drain regions to be heavier than in the channel region, the patent simultaneously achieves high electron mobility in the channel and reduced leakage current at the contacts, resolving the technical contradiction.
2Object-generated harmful factors
If channel length is increased to reduce leakage current, then leakage current decreases, but device area increases
Solution Approach 1:
Instead of changing the geometric parameter (channel length), the patent changes the doping concentration parameter in the source and drain regions. This allows leakage current reduction through electrical parameter optimization rather than geometric expansion, thus reducing device area while maintaining low leakage performance.
3Object-generated harmful factors
If lightly doped regions are added at sides of channel, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent segments the active layer into distinct regions with different doping concentrations: lightly doped channel region and heavily doped source/drain regions. This segmentation allows independent optimization of each region's properties, reducing leakage current while maintaining a manageable structural complexity through clear regional differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces leakage current, allowing for high PPI displays by optimizing the doping concentrations and regions, thereby improving the aperture ratio and display quality without significant power consumption increase.
Implementation Method 1
a part of the active layer overlapped with the opening includes a first lightly doped region, a first heavily doped region and a second lightly doped region which are sequentially arranged
Data Source
AI summary
A thin film transistor and a manufacturing method therefor, an array substrate, and a display device. The thin film transistor includes an active layer, a gate insulating layer, and a gate electrode; the gate insulating layer is located on one side of the active layer; the gate electrode is located on one side of the gate insulating layer distant from the active layer; the gate electrode includes an opening a part of the active layer overlapped with the opening includes a first lightly doped region, a first heavily doped region, and a second lightly doped region that are sequentially arranged along a first direction parallel to a plane where the active layer is located.