Self-Aligned TFT Gate Overhangs for Parasitic Capacitance
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Solution Overview
Problem
Current methods for manufacturing amorphous silicon thin-film transistors (a-Si:H TFTs) face challenges in achieving the desired overlap between source/drain and gate regions, leading to parasitic capacitance and degradation in device switching speed and latency.
Innovation Solution
A self-aligning, self-patterning process is employed, where overhang regions are formed through selective etching of a dielectric/gate metal stack, allowing for the deposition of conductive layers with 'tails' that extend into these overhangs, creating a conduction path while maintaining electrical isolation and accommodating thermal stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If photolithographic processes are used to form source, gate and drain regions, then electrical connection is achieved, but parasitic capacitance increases due to excessive overlap between source/drain and gate regions
Solution Approach 1:
The gate region is formed first as an etch stop layer before forming the source and drain regions. This preliminary positioning of the gate allows precise control of the overlap distance between source/drain and gate regions, ensuring optimal carrier injection while minimizing parasitic capacitance by preventing excessive overlap.
Solution Approach 2:
The patent replaces traditional photolithographic alignment methods with a self-aligned etching process. The gate region itself serves as the alignment reference for forming source and drain regions through selective etching, eliminating the need for separate photolithographic alignment steps and providing more precise control over overlap dimensions.
2Reliability
If overlap between source/drain and gate regions is increased to provide conductivity, then carrier injection is improved, but device switching speed degrades due to parasitic capacitance
Solution Approach 1:
The gate region is pre-formed as an etch stop layer with precisely controlled dimensions before source and drain regions are created. This allows the overlap distance to be optimized in advance to provide sufficient carrier injection while maintaining small enough overlap to minimize parasitic capacitance and preserve switching speed.
Solution Approach 2:
The patent precisely controls the overlap distance parameter between source/drain and gate regions through the etch stop layer mechanism. By adjusting this geometric parameter, the system achieves optimal balance between carrier injection efficiency and parasitic capacitance minimization, thereby maintaining high switching speed.
3Ease of manufacture
If multiple photolithographic and deposition steps are used to form TFT arrays, then device structure is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple separate fabrication steps into a unified self-aligned process. The gate region formation serves simultaneously as gate electrode creation and as the alignment reference for subsequent source/drain region formation through selective etching, eliminating the need for separate photolithographic alignment steps and reducing overall manufacturing complexity.
Solution Approach 2:
The gate region automatically serves as the alignment reference for forming source and drain regions. The etch stop layer mechanism provides self-alignment without requiring external photolithographic patterning steps, allowing the structure to define its own geometric relationships and simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables optimal carrier injection with reduced parasitic capacitance and improved device performance by allowing for controlled overlap between source/drain and gate regions, enhancing the switching speed and reliability of TFTs.
Implementation Method 1
Selective etching of the dielectric/gate metal stack results in an over-etching of the dielectric and an undercutting of the gate metal, forming overhang regions.
Implementation Method 2
A subsequently deposited doped conductive layer forms source and drain regions, with 'tails' which extend into the overhang regions.
Data Source
AI summary
A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.