TFT Gate Electrode Overlap Reduction via Segmented Contact Holes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In organic light emitting diode (OLED) displays, the overlapping of source and drain electrodes with the gate electrode leads to parasitic capacity, causing signal delay and reduced image quality due to insufficient charging of storage capacitors in thin film transistors (TFTs).
Innovation Solution
The design of TFTs with strategically placed contact holes that expose only partial surfaces of the oxide semiconductor layer, allowing the source and drain electrodes to contact specific parts while minimizing overlap with the gate electrode, thereby reducing parasitic capacity and signal delay. This design includes a first and second set of contact holes for the switching and driving TFTs, respectively, with the source and drain electrodes covering these holes to maintain efficient signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source and drain electrodes cover contact holes to contact oxide semiconductor layer, then electrical connection is achieved, but parasitic capacity increases causing signal delay
Solution Approach 1:
The contact holes are segmented into multiple types (first contact holes exposing first parts of oxide semiconductor layer, second contact holes exposing second parts). The source and drain electrodes are divided into corresponding segments that contact different parts of the oxide semiconductor layer through different contact holes, reducing overlapping area with gate electrode while maintaining electrical connection
Solution Approach 2:
Different regions of the oxide semiconductor layer are exposed through different contact holes to create local contact points. The source electrode contacts the oxide semiconductor layer through first contact holes at one location, while the drain electrode contacts through second contact holes at another location, optimizing the local electrical connection properties and minimizing parasitic capacity in each region
2Reliability
If source and drain electrodes overlap gate electrode, then contact area is increased, but parasitic capacity in gate insulation layer increases
Solution Approach 1:
The contact holes penetrate through the gate insulation layer to expose the oxide semiconductor layer, creating vertical contact paths. This dimensional approach allows electrical connection through the insulation layer without requiring lateral overlap of source/drain electrodes with the gate electrode, thereby reducing parasitic capacity while maintaining contact area
Solution Approach 2:
The gate insulation layer is designed with contact holes that act as intermediaries, allowing the source and drain electrodes to contact the oxide semiconductor layer through these openings. This intermediary structure enables electrical connection without direct overlap between source/drain electrodes and gate electrode, reducing parasitic capacity in the gate insulation layer
Data Source
AI summary
A thin film transistor (TFT) includes a gate electrode disposed on a substrate. An oxide semiconductor layer is disposed on the gate electrode. An insulation layer is disposed on the oxide semiconductor layer. The insulation layer includes a first contact hole that exposes a first part of the oxide semiconductor layer corresponding to a first end of the gate electrode and a second contact hole that exposes a second part of the oxide semiconductor layer corresponding to an opposite end of the gate electrode. A source electrode is disposed on the insulation layer and contacts the first part of the oxide semiconductor layer through the first contact hole. A drain electrode is disposed on the insulation layer and contacts the second part of the oxide semiconductor layer through the second contact hole.