Thin Film Transistor Array Panel Gate Pad Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In thin film transistor array panels, the shrinking interval between gate and data pads makes it difficult to form and read identification numbers, leading to defects during inspection and wire pressing, as well as a risk of pad shorting.
Innovation Solution
The solution involves forming gate and data identification members on the same layer as the pads, with these members being oriented along the major axis of the pads and partially overlapping with contact assistants, allowing for easy identification without creating steps that could lead to defects during the press process and reducing the risk of pad shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If identification numbers are formed between gate pads or data pads to enable defect inspection, then identification capability is improved, but the risk of pad shorting increases and manufacturing precision deteriorates due to step generation during pressing
Solution Approach 1:
The identification function is extracted from the space between pads and relocated to separate identification members positioned adjacent to each pad. This separation eliminates the risk of pad shorting while maintaining identification capability, as the identification members are formed in the same layer as the pads but do not occupy the critical spacing between adjacent pads.
Solution Approach 2:
Identification members are introduced as intermediary elements that provide defect inspection capability without directly interacting with the electrical pads. These members are formed in the same layer but positioned adjacent to pads, serving as mediators that enable identification while maintaining proper pad spacing and preventing shorting.
2Reliability
If identification numbers are formed in narrow spaces between neighboring pads to prevent shorting, then pad shorting risk is reduced, but the numbers become too small to read easily and manufacturing precision deteriorates
Solution Approach 1:
The identification members are positioned in a different spatial arrangement - adjacent to pads rather than between them - effectively utilizing the lateral dimension along the pad row. This dimensional repositioning allows for larger, more readable identification members while maintaining adequate spacing to prevent pad shorting.
3Loss of information
If identification numbers are formed with different material from gate pads, then identification capability is improved, but step generation occurs during pressing process causing defects
Solution Approach 1:
The identification members are formed of the same material as the gate pads and data pads, ensuring material homogeneity across the pad layer. This eliminates step generation during the pressing process, as there are no material interface differences, while still providing clear identification capability through the distinct positioning and pattern of the identification members.
Data Source
AI summary
A thin film transistor array panel can include: a substrate; a gate line formed on the substrate; a gate pad formed at an end of the gate line; a gate identification member corresponding to the gate pad and formed in the same layer as the gate pad; a gate insulating layer covering the gate line and the gate identification member; a data line formed on the gate insulating layer; a passivation layer formed on the gate insulating layer and the data line; a gate contact assistant formed on the passivation layer; and a gate driving chip electrically connected to the gate contact assistant, wherein the gate contact assistant at least partially overlaps the gate identification member. The gate identification member is formed without producing a step in the gate contact assistant, reducing the risk of defects when wires or other objects are pressed onto the gate pad.