Top-Gated Thin Film Transistor Gate Patterning via Segmented Photoresist Masking
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Solution Overview
Problem
Conventional methods for manufacturing top-gated thin film transistors often result in over-etched gate metal layers, leading to reduced current between the source and drain, and compromised device performance due to inadequate control over the conductive channel.
Innovation Solution
A method involving the formation of a specific photoresist pattern with a first shielding portion and second shielding portions, where the first photoresist pattern is used as a mask for etching the gate metal layer, ensuring the gate pattern size aligns with the channel region, and subsequent ashing and conductorizing processes to form contact regions, enhancing gate control and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used on gate metal layer, then manufacturing process is simple, but gate pattern width becomes smaller than channel region width due to over-etching, resulting in reduced gate control and decreased current
Solution Approach 1:
The photoresist layer is segmented into multiple portions (first photoresist pattern and second photoresist pattern) with different functions. The first photoresist pattern serves as etching mask for gate metal layer, while the second photoresist pattern serves as etching mask for gate insulation layer. This segmentation allows precise control of gate pattern width without over-etching, resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The first photoresist pattern is formed in advance with a width larger than the desired gate pattern width. This preliminary action provides a protective mask during etching that prevents over-etching, ensuring the gate pattern width matches the channel region width exactly, thereby improving manufacturing precision.
2Ease of manufacture
If gate metal layer is over-etched to simplify manufacturing, then etching process is easier, but gate cannot completely control conductive channel, reducing device performance
Solution Approach 1:
The first photoresist pattern acts as an intermediary protective mask during the etching of gate metal layer. It prevents direct over-etching of the gate metal layer by providing a controlled etching boundary, thereby maintaining gate control reliability while still allowing the etching process to proceed efficiently.
3Productivity
If single photoresist pattern is used for both gate and source/drain etching, then manufacturing steps are reduced, but gate pattern width cannot be precisely controlled
Solution Approach 1:
The photoresist pattern is segmented into first and second portions with different widths and functions. The first photoresist pattern (wider) controls gate pattern width during gate metal etching, while the second photoresist pattern (narrower) controls source/drain region etching. This segmentation enables precise gate pattern width control while maintaining reasonable manufacturing efficiency through sequential processing.
Solution Approach 2:
Different portions of the photoresist layer are given different local qualities (widths and positions). The first photoresist pattern has a larger width to protect gate metal layer edges, while the second photoresist pattern has a smaller width for source/drain etching. This local differentiation enables precise control of gate pattern width without significantly increasing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures precise control of the gate pattern size over the channel region, thereby improving the operational speed and performance of top-gated thin film transistors by maintaining current integrity and reducing parasitic capacitance.
Implementation Method 1
The patterning process for the photoresist layer to form the first photoresist pattern includes: exposing the photoresist layer by adopting a halftone mask, and developing the exposed photoresist layer by a developing solution to form the first photoresist pattern
Implementation Method 2
performing an ashing process for the second shielding portion of the first photoresist pattern by adopting oxygen
Data Source
AI summary
A method for manufacturing the top-gated thin film transistors is disclosed and includes forming a first photoresist pattern with a first shielding portion and two second shielding portions, and etching a gate metal layer by adopting the first photoresist pattern as a mask. Thus, a size of the gate pattern coincides with a size of a channel region of a conductive channel, to increase a control force of a gate to the conductive channel, thereby improving performance of device.