Thin Film Transistor Gate Electrode Segmentation for Stray Capacitance Reduction
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Solution Overview
Problem
Conventional thin film transistors face issues with uniformity due to poor electrode alignment and increased stray capacitance from overlapping electrodes, which affect electrical properties and operation speed, while a single dielectric layer is insufficient for modern integrated circuits.
Innovation Solution
A thin film transistor structure with a thin first insulating layer and a thicker second insulating layer, using high permittivity materials for the first layer and low permittivity materials for the second layer, to optimize electrode alignment and reduce stray capacitance, along with a manufacturing method that involves specific thickness standards for these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electrodes are separated without overlapping, then alignment uniformity is improved, but minimum gate line width resolution is limited
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) that are separated by a gap, allowing each segment to be independently formed with precise width control while maintaining overall gate functionality
Solution Approach 2:
The gate electrode structure transitions from a single continuous layer to a multi-layer segmented structure, adding vertical dimensionality through the first and second gate electrode layers to achieve both precision and resolution
2Reliability
If electrodes are made to overlap, then photocurrent problem is prevented, but stray capacitance increases and operation speed decreases
Solution Approach 1:
The harmful stray capacitance effect is extracted and eliminated by separating the gate electrode into non-overlapping segments, while the beneficial photocurrent prevention is maintained through the segmented structure's geometric configuration
Solution Approach 2:
The gate electrode geometry parameters are changed from continuous overlap to segmented separation, fundamentally altering the electrical field distribution to reduce capacitance while maintaining photovoltaic performance
3Object-generated harmful factors
If dielectric layer thickness is increased to reduce stray capacitance, then capacitance is reduced, but conduction current decreases and transistor performance is affected
Solution Approach 1:
The gate electrode is segmented into multiple layers and sections, allowing the dielectric layer thickness to be optimized for capacitance reduction in non-overlapping regions while maintaining adequate conduction current through the segmented structure
Solution Approach 2:
Different regions of the gate structure have different dielectric thickness requirements - the first and second gate electrode regions are designed with specific thicknesses to locally optimize both capacitance reduction and current conduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operation speed of the transistor by minimizing stray capacitance and maintaining conduction current, addressing the limitations of single dielectric layers in modern integrated circuits.
Implementation Method 1
the overlapped electrodes will produce stray capacitance, which slows down the transistor operation speed
Implementation Method 2
using high permittivity materials for the first layer and low permittivity materials for the second layer
Data Source
AI summary
A thin film transistor is disclosed. The drain and source electrode layer of the thin film transistor is disposed on the substrate, in which the drain and source electrode layer is divided into a drain region and a source region. The semiconductor layer and the first insulating layer are disposed on the drain and source electrode layer, in which the first insulating layer has an upper limit of thickness. The second insulating layer is disposed on the semiconductor layer and the first insulating layer, in which the second insulating layer has a lower limit of thickness. The gate electrode layer is disposed on the second insulating layer. The passivation layer is disposed on the gate electrode layer, and the pixel electrode layer is disposed on the passivation layer.