Bottom-gate TFT Gate Sidewall Spacer Relaxing Electric Field
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Solution Overview
Problem
Existing thin film transistors suffer from a local concentration of electric field near the gate edge, leading to kink current and reliability degradation, which is not adequately addressed by existing LDD configurations.
Innovation Solution
A thin film transistor design with a semiconductor layer that forms a linear or substantially linear shape at the boundary between regions of varying distance from the gate electrode, allowing for a gradual change in potential and reducing electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate and drain are spaced further apart with an LDD configuration, then the electric field concentration is partially reduced, but the relaxation is insufficient and kink current still occurs
Solution Approach 1:
The patent applies local quality by creating distinct regions within the semiconductor layer with different doping concentrations and thicknesses. Specifically, a first semiconductor layer region with lower doping concentration and a second semiconductor layer region with higher doping concentration are formed at different locations relative to the gate electrode. This localized variation in material properties allows the electric field to be distributed more evenly, reducing concentration at critical points while maintaining overall device functionality.
Solution Approach 2:
The patent introduces a vertical dimension to the semiconductor layer structure by forming a gate sidewall spacer that extends vertically from the gate electrode. This three-dimensional structure creates multiple regions (first, second, and third semiconductor layer regions) at different vertical and horizontal positions. The gate sidewall spacer acts as a buffer that gradually transitions the electric field from the high-concentration gate region to the drain region, effectively reducing field concentration through spatial distribution in multiple dimensions.
2Ease of manufacture
If a simple LDD configuration is used, then the device structure remains relatively simple, but the local electric field concentration near the gate edge is not adequately relaxed
Solution Approach 1:
The gate sidewall spacer serves as an intermediary structure between the gate electrode and the drain region. This spacer is formed by depositing insulating material on the side surface of the gate electrode, creating a physical buffer zone. The intermediary structure allows for a gradual transition of the electric field rather than an abrupt change, effectively mediating the field distribution and reducing concentration at the gate edge while maintaining manufacturing feasibility through standard deposition processes.
Solution Approach 2:
The semiconductor layer is segmented into multiple distinct regions with different properties: a first region with lower doping concentration, a second region with higher doping concentration, and a third region positioned vertically above the gate. This segmentation allows each region to serve a specific function in managing the electric field distribution. The segmented structure achieves better field relaxation than a uniform LDD configuration while using conventional manufacturing techniques to form each segment separately.
Data Source
AI summary
Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.