Thin Film Transistor Gate Electrode Work Function Engineering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in enhancing the resolution of liquid crystal display panels, such as 8K displays, is the need to downsize thin film transistors (TFTs) and thin gate bus wiring while maintaining or improving the aperture ratio without degrading the switching characteristics, which is hindered by the short channel effect causing a decrease in gate threshold and increased off current.
Innovation Solution
A thin film transistor design featuring a gate electrode with a laminated structure of different work function materials and a low concentration impurities region in the semiconductor layer, formed using amorphous silicon, which helps maintain the gate threshold and reduce off current even when the channel length is shortened, allowing for thinner wiring and improved aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length is shortened to downsize the TFT, then the TFT size is reduced and the aperture ratio is improved, but the gate threshold decreases due to the short channel effect and off current increases
Solution Approach 1:
The patent applies local quality by creating a multi-layer gate electrode structure where different layers have different work functions. The first gate electrode layer has a first work function and the second gate electrode layer has a second work function, allowing different regions of the gate to provide different electrical characteristics. This enables compensation for the short channel effect locally at the gate level while maintaining the shortened channel length for compact TFT size.
Solution Approach 2:
The patent uses composite materials by combining multiple gate electrode layers with different work functions. This composite gate structure allows the device to achieve both the shortened channel length needed for downsizing and the appropriate gate threshold control needed for reliable switching characteristics, effectively resolving the technical contradiction between size reduction and performance maintenance.
2Area of moving object
If the gate bus wiring is thinned to enable higher pixel density, then the aperture ratio is improved, but the patterning accuracy becomes difficult to maintain
Solution Approach 1:
The patent resolves the patterning accuracy issue by transitioning from a single-layer gate electrode to a multi-layer gate electrode structure. This dimensional change in the gate electrode configuration allows the use of standard photolithography processes to achieve the required precision, as the multi-layer structure provides better process margins and alignment tolerance compared to attempting to pattern a single ultra-thin gate bus wiring layer.
3Volume of moving object
If the channel length is shortened to downsize the TFT, then the TFT area is reduced, but the gate threshold decreases and switching characteristics deteriorate
Solution Approach 1:
The patent applies parameter changes by modifying the work function parameters of the gate electrode layers. By selecting materials with appropriate work functions for the first and second gate electrode layers, the patent can control the effective gate threshold voltage. This allows the device to maintain proper switching characteristics even with the shortened channel length, as the work function parameters are optimized to compensate for the reduced channel dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the downsizing of TFTs and thinning of gate bus wiring without degrading the switching characteristics, maintaining or improving the aperture ratio and enabling higher pixel density in display panels.
Implementation Method 1
The gate electrode comprises a first layer having a first work function and a second layer having a second work function, the second layer being interposed between the first layer and the gate insulating layer; the second work function is less than the first work function in a case that the impurities are n-type impurities, while the second work function is greater than the first work function in a case that the impurities are p-type impurities
Implementation Method 2
the semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region containing impurities in a predetermined low concentration and being formed in separation from the gate insulating layer
Data Source
AI summary
A thin film transistor according to one embodiment comprises a gate electrode; a semiconductor layer being formed using amorphous silicon and comprising a region overlapping with the gate electrode; a gate insulating layer; and a source electrode and a drain electrode facing each other with a predetermined interval therebetween. The gate electrode comprises a first layer having a first work function; and a second layer having a second work function and being interposed between the first layer and the gate insulating layer. The semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region. The second work function is less than the first work function when n-type impurities are contained in the low concentration impurities region, while the second work function is greater than the first work function when p-type impurities are contained in the low concentration impurities region.