Thin Film Transistor Gettering for Leakage Reduction
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Solution Overview
Problem
Existing methods for crystallizing amorphous silicon (a-Si) layers using metal catalysts often result in high leakage currents due to residual metal catalysts in the semiconductor layer, which degrade the electrical properties of OLED display devices and thin film transistors (TFTs).
Innovation Solution
A method involving the formation of external gettering sites and connection portions to effectively remove remaining metal catalysts from the semiconductor layer, utilizing a capping layer and controlled metal catalyst diffusion to minimize catalyst concentration, followed by annealing to facilitate the gettering process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal catalyst is used to crystallize amorphous silicon layer, then crystallization temperature is reduced and processing time is shortened, but metal catalyst remains in the semiconductor layer causing high leakage current
Solution Approach 1:
The patent applies the extraction principle by introducing a dedicated gettering region that selectively removes metal catalyst impurities from the semiconductor layer. The gettering region acts as a trap that extracts residual metal catalysts (such as nickel, palladium, or platinum) from the crystallized poly-Si layer, thereby reducing leakage current while maintaining the benefits of rapid crystallization processes.
Solution Approach 2:
The patent uses a gettering region as an intermediary element between the semiconductor layer and the metal catalyst impurities. This intermediary structure facilitates the removal of harmful metal catalysts without affecting the functional properties of the semiconductor device, effectively mediating the conflict between rapid crystallization and low leakage current requirements.
2Reliability
If conventional gettering methods using phosphorus gas or noble gas are used, then some metal catalyst is removed, but metal catalyst is not effectively removed and leakage current remains problematic
Solution Approach 1:
The patent converts the harmful presence of metal catalyst impurities into a beneficial process by designing a gettering region that intentionally attracts and traps these impurities. The gettering region transforms the problematic metal catalyst residues into a concentrated form within the gettering structure, effectively removing them from the functional semiconductor layer and significantly reducing leakage current.
3Speed
If excimer laser annealing is used for crystallization, then high speed crystallization is achieved, but protrusions form on the poly-Si layer surface degrading interface characteristics
Solution Approach 1:
The patent removes the harmful surface protrusions caused by excimer laser annealing by introducing a gettering region that selectively extracts the malformed surface material and metal catalyst impurities. This extraction process restores the平整ness of the poly-Si layer surface, improving interface characteristics with the gate insulating layer while maintaining the high-speed crystallization advantage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the amount of metal catalyst remaining in the semiconductor layer, thereby improving the electrical properties and reducing leakage currents in OLED display devices and TFTs.
Implementation Method 1
a metal catalyst remaining in a channel region of a semiconductor layer which is crystallized using the metal catalyst is gettered
Implementation Method 2
annealing to facilitate the gettering process
Data Source
AI summary
A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain electrodes disposed on the pixel region, at least one gettering site disposed on the non-pixel region, and at least one connection portion to connect the at least one gettering site and the semiconductor layer The method of fabricating the TFT includes patterning a polycrystalline silicon (poly-Si) layer to form a plurality of semiconductor layers, connection portions, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the connection portions, and annealing the substrate to getter the plurality of semiconductor layers.