TFT Metal Catalyst Gettering via Source Drain Electrodes
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Solution Overview
Problem
Existing methods for crystallizing amorphous silicon into polycrystalline silicon for thin film transistors (TFTs) face issues such as long processing times, substrate deformation, high costs, and contamination from metal catalysts, leading to degraded device characteristics and increased leakage current.
Innovation Solution
A bottom-gate TFT is fabricated using a metal catalyst layer, where the channel region is gettered using the source/drain electrode material layer as a gettering site, with a second metal or its silicide diffused into the semiconductor layer under the electrodes to reduce metal catalyst presence, thereby improving electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a metal catalyst is used to crystallize the a-Si layer, then the crystallization temperature is reduced and processing time is shortened, but metal catalyst contamination remains in the poly-Si layer causing increased leakage current
Solution Approach 1:
The patent extracts the harmful metal catalyst from the channel region by introducing a gettering site that selectively absorbs and traps the metal catalyst, separating the beneficial crystallization function from the harmful contamination effect
Solution Approach 2:
The patent introduces a gettering site as an intermediary element between the metal catalyst and the channel region, which mediates the interaction by capturing the metal catalyst before it can contaminate the active device area
2Object-generated harmful factors
If a conventional gettering process is performed using impurities or additional a-Si layers, then some metal catalyst removal is attempted, but the metal catalyst is not effectively removed and leakage current remains large
Solution Approach 1:
The patent employs the source/drain electrode material layer to serve dual functions: as the electrical contact structure and as the gettering site for metal catalyst removal, eliminating the need for separate gettering structures
Solution Approach 2:
The patent merges the source/drain electrode function with the gettering function into a single integrated structure, combining electrical connectivity with contamination removal capabilities
3Stability of the object's composition
If the a-Si layer is annealed at high temperature for long period (SPC method), then the a-Si layer is crystallized into poly-Si, but the substrate is deformed and processing time is excessive
Solution Approach 1:
The patent changes the crystallization parameters by using metal catalyst-assisted crystallization at lower temperatures and shorter times, fundamentally altering the thermal processing conditions from high-temperature long-duration to low-temperature short-duration
4Ease of manufacture
If the gettering site is located far from the channel region, then the fabrication process is simplified, but the effectiveness of metal catalyst removal is reduced
Solution Approach 1:
The patent positions the gettering site in a spatially optimal location adjacent to the channel region, utilizing the vertical and lateral dimensions effectively to maximize metal catalyst capture while maintaining fabrication simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces metal catalyst contamination in the channel region, enhancing the electrical properties of the TFT and reducing leakage current, while simplifying the fabrication process and avoiding substrate deformation.
Implementation Method 1
A channel region of a semiconductor layer, which is crystallized using a metal catalyst layer, is gettered using a source/drain electrode material layer as a gettering site
Implementation Method 2
A second metal, or a silicide of the second metal, is diffused into a surface region of the semiconductor layer, under the source and drain electrodes, to a predetermined depth
Implementation Method 3
a metal, such as nickel (Ni), palladium (Pd), gold (Au), or aluminum (Al), is brought into contact with, or doped into, an a-Si layer to induce a phase change of the a-Si layer into a poly-Si layer
Data Source
AI summary
A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer and crystallized using a metal catalyst, and source and drain electrodes disposed on the semiconductor layer and electrically connected to source and drain regions of the semiconductor layer. A second metal is diffused into a surface region of the semiconductor layer, to getter the metal catalyst from a channel region of the semiconductor layer. The second metal can have a lower diffusion coefficient in silicon than the metal catalyst.