Thin Film Transistor Channel Grain Boundary Control
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Solution Overview
Problem
Existing methods for fabricating polycrystalline silicon layers for thin film transistors face challenges in controlling the concentration and position of crystallization catalysts, leading to issues with seed formation, grain boundaries, and uniformity, which affect the characteristics and performance of thin film transistors.
Innovation Solution
A method is developed to form a semiconductor layer pattern with a channel layer that either has no seed and no grain boundary or a controlled number of grain boundaries, using a capping layer and metal catalyst diffusion to crystallize the amorphous silicon layer, with specific dimensions and crystallinity ratios to enhance transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If metal catalyst is diffused through capping layer to crystallize amorphous silicon, then crystallization temperature is reduced and crystallization speed is improved, but metal contamination of thin film transistor characteristics deteriorates
Solution Approach 1:
The invention divides the capping layer into multiple segments with different metal catalyst concentrations. The first capping layer has a first metal catalyst concentration, while the second capping layer has a second metal catalyst concentration that is lower than the first. This segmentation allows controlled diffusion of metal catalysts at different levels, reducing overall metal contamination while maintaining effective crystallization at lower temperatures.
Solution Approach 2:
The invention applies local quality by creating non-uniform metal catalyst distribution within the capping layer structure. Different regions (first and second capping layers) have different metal catalyst concentrations tailored to their specific functions - the first layer provides sufficient catalyst for crystallization initiation, while the second layer provides reduced contamination for the transistor channel region.
2Object-affected harmful factors
If metal catalyst concentration is reduced to minimize contamination, then metal contamination is reduced, but uniformity of crystallization and control of grain size become difficult
Solution Approach 1:
The capping layer is segmented into two distinct layers with different metal catalyst concentrations. The first capping layer contains a higher concentration to ensure reliable crystallization initiation and uniform grain formation, while the second capping layer contains a lower concentration to reduce metal contamination in the transistor active region. This segmentation simultaneously achieves both low contamination and good crystallization uniformity.
Solution Approach 2:
Different regions of the capping layer are assigned different metal catalyst concentrations based on local requirements. The first capping layer (closer to the amorphous silicon) has higher catalyst concentration for effective crystallization, while the second capping layer (closer to the transistor channel) has lower concentration for reduced contamination. This local quality approach ensures optimal crystallization uniformity where needed while minimizing contamination elsewhere.
3Device complexity
If seed formation is allowed to occur naturally, then crystallization process is simplified, but number of grain boundaries increases and transistor characteristics become non-uniform
Solution Approach 1:
The invention performs preliminary action by forming a structured capping layer with controlled metal catalyst distribution before the crystallization process. The first and second capping layers are deposited with specific metal catalyst concentrations that pre-determine the crystallization behavior. This preliminary structuring guides the crystallization process to produce uniform grains with minimal boundaries in the transistor channel, eliminating the need for post-crystallization seed management.
Solution Approach 2:
The capping layer structure provides local quality control for seed formation. The first capping layer region allows controlled seed initiation with adequate metal catalyst, while the second capping layer region suppresses excessive seed formation and grain boundary creation near the transistor channel. This local differentiation ensures uniform transistor characteristics without requiring complex post-processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved uniformity and performance of thin film transistors by controlling the crystallization catalyst concentration and position, resulting in enhanced characteristics and reduced metal contamination, suitable for applications in LCD and OLED devices.
Implementation Method 1
diffusing a metal catalyst of the metal catalyst layer into the amorphous silicon layer
Implementation Method 2
crystallizing the amorphous silicon layer using the diffused metal catalyst
Implementation Method 3
thermal annealing or laser annealing
Data Source
AI summary
A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern which is formed on the substrate, the semiconductor layer pattern having a channel layer of which no seed exists and no grain boundary exists; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film. A method for fabricating the thin film transistor includes forming an amorphous silicon layer on a substrate; forming a semiconductor layer pattern having a channel layer in which no seed exists and no grain boundary exists by crystallizing and patterning the amorphous silicon layer; forming a gate insulating film on the semiconductor layer pattern; and forming a gate electrode on the gate insulating film.