Thin Film Transistor Gray Scale Photoresist Patterning
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Solution Overview
Problem
Conventional methods for manufacturing thin film transistors require numerous photolithographic and etching steps, making the process costly and inefficient.
Innovation Solution
A method involving the use of a gray scale photoresist pattern that overlaps specific regions of a layered structure, allowing for isotropic stripping and anisotropic etching to form a gate electrode, reducing the number of photolithographic/etching steps required, and enabling doping of source and drain regions with varying dopant concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic and etching steps are used to form thin film transistors, then manufacturing precision is maintained, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent combines multiple photolithographic and etching steps into a single integrated process. A gray-scale photoresist pattern is formed that simultaneously defines gate, source, and drain regions, allowing all three regions to be created in one exposure and development cycle rather than requiring separate steps for each region.
Solution Approach 2:
The patent introduces grayscale variation in the photoresist layer as an additional dimensional parameter. By controlling the thickness or optical density of the photoresist in different regions, the patent creates different etch rates or doping concentrations, enabling multi-region definition within a single photoresist layer without requiring multiple patterning steps.
2Reliability
If multiple photolithographic and etching steps are employed, then transistor quality is maintained, but productivity decreases due to extended processing time
Solution Approach 1:
The patent performs preliminary patterning by forming a gray-scale photoresist pattern that pre-defines all subsequent regions (gate, source, drain) in a single step. This preliminary action eliminates the need for multiple sequential patterning operations, reducing total processing time while maintaining the precision required for high-quality transistor formation.
Solution Approach 2:
The patent enables continuous processing by eliminating idle time between multiple photolithographic and etching steps. The single gray-scale photoresist pattern allows all regions to be defined and processed in a continuous workflow without requiring intermediate steps, thereby increasing manufacturing throughput while preserving transistor quality.
3Manufacturing precision
If conventional multi-step patterning is used, then source and drain region definition is achieved, but manufacturing cost increases due to excessive process steps
Solution Approach 1:
The patent merges the definition of source, drain, and gate regions into a single photolithographic step using a gray-scale photoresist pattern. This consolidation eliminates multiple expensive photolithography and etching steps while maintaining precise regional definition through grayscale-controlled patterning.
Solution Approach 2:
The patent changes the parameter of photoresist optical density or thickness to create grayscale variations. By controlling these parameters during photoresist formation, the patent achieves different pattern definitions in different regions without requiring multiple exposure or development steps, thereby reducing manufacturing cost while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces manufacturing costs by minimizing the number of photolithographic/etching steps, while maintaining the quality of thin film transistors suitable for applications like LCDs and OLEDs.
Implementation Method 1
stripping the first gray scale photoresist pattern isotropically to cause thinning of the first gate defining region of the first gray scale photoresist pattern and removal of the first source defining region and the first drain defining region
Implementation Method 2
etching the gate-forming layer anisotropically so as to remove the first source covering region and the first drain covering region of the gate-forming layer from the dielectric layer after step (e) to form a first gate electrode of the gate-forming layer
Data Source
Figure 1
Figure 2A~2C
Figure 2D~2F
AI summary
A method of making a thin film transistor device includes: forming a semiconductor layer (51), a dielectric layer (52), and a gate-forming layer (53) on the dielectric layer (52) to define a layered structure (50), forming a gray scale photoresist pattern (54) on the gate-forming layer (53), stripping the gray scale photoresist pattern (54) isotropically to cause removal of source and drain defining regions (542, 543), etching the gate-forming layer (53) anisotropically so as to remove source and drain covering region (532, 533), doping a first type dopant into source and drain regions (511, 512), and removing a gate defining region (541) from the gate-forming layer (53).