TFT Array Groove Conducting Lines Low Resistance
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Solution Overview
Problem
As display panels increase in size and resolution, the addressing time of pixels becomes shorter, leading to high line resistance and capacitance loading, which decreases charging efficiency in TFT-driven displays.
Innovation Solution
A pixel structure is developed with a switching element and storage capacitor on a substrate, utilizing high-k dielectric layers and conducting lines formed in grooves on the substrate, along with a low-k dielectric layer at cross-overs to reduce line resistance and capacitance loading, and a source line segmented for improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of the display panel becomes large and resolution becomes high, then the display quality is improved, but the line resistance of addressing lines becomes very high
Solution Approach 1:
The source line is divided into multiple source line segments, and the gate line is divided into multiple gate line segments. This segmentation allows for shorter individual line lengths, reducing the cumulative resistance while maintaining the ability to address all pixels in high-resolution displays.
Solution Approach 2:
Conducting lines are formed in grooves on the substrate surface, creating a three-dimensional structure. This allows addressing lines to route through the substrate depth rather than only on the surface, shortening the effective path length and reducing resistance for high-resolution displays.
2Area of stationary object
If the size of the display panel becomes large, then the display area is increased, but the addressing time of pixels becomes very short
Solution Approach 1:
By segmenting the source and gate lines into multiple shorter segments, the RC time constant for each segment is reduced, allowing faster charging of pixel electrodes across large display areas while maintaining short addressing times.
Solution Approach 2:
High-k dielectric layers are selectively placed at critical locations such as storage capacitor regions and transistor gate regions, providing enhanced capacitance and transconductance locally to speed up pixel addressing across the entire large display area.
3Measurement precision
If the resolution becomes high, then the pixel density is increased, but the capacitance loading of the display panel becomes high
Solution Approach 1:
High-k dielectric materials with dielectric constants of 8 or greater are used in storage capacitors and transistor gates, increasing the capacitance density. This allows smaller capacitor structures that reduce total loading while maintaining required charge storage for high-resolution pixels.
Solution Approach 2:
Storage capacitors are integrated within the pixel area using overlapping electrode structures and high-k dielectrics, effectively nesting the capacitor function within the pixel footprint. This reduces the area required per pixel and decreases total capacitance loading for high-resolution displays.
4Ease of manufacture
If conventional conducting lines are used, then the manufacturing process is simple, but the line resistance is very high
Solution Approach 1:
Conducting lines are formed in grooves on the substrate surface using standard semiconductor fabrication techniques. This three-dimensional configuration shortens the effective line length and reduces resistance while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The conducting lines use composite structures combining conductive materials filled in groove structures, creating low-resistance pathways that maintain ease of manufacture through standard deposition and filling processes while achieving significantly reduced line resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pixel structure enhances transconductance and storage capacitance, reducing line resistance and capacitance loading, thereby improving the charging efficiency of display pixels.
Implementation Method 1
The high-k dielectric layer has a dielectric constant equal to or greater than 8
Implementation Method 2
The high-k dielectric layer has a dielectric constant equal to or greater than 8
Implementation Method 3
the low-k dielectric layer has a dielectric constant equal to or lower than 3.5
Data Source
AI summary
A pixel structure in a pixel for used in a display panel has a plurality of grooves made on a substrate and a plurality of conducting lines formed in the grooves. The conducting line can be made from a silver or copper conductive ink to provide a low-resistance line served as a gate line, common line or source line. In a pixel having a storage capacitor and a TFT with a gate electrode, a source electrode and a drain electrode, the gate electrode is connected to a gate line and a source electrode and one of the capacitor electrodes in the storage capacitor is connected to a common line. At least part of one or more of the gate electrode and the source electrode is disposed on top of and in contact with the surface of one or more conducting lines.