TFT Array Substrate With Heterogeneous Conductorization Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing thin film transistor (TFT) technologies face challenges in manufacturing, including high production costs, complex processes, and difficulties in achieving uniformity and reducing parasitic capacitance, especially when forming a capacitor with a thin thickness.
Innovation Solution
A thin film transistor array substrate structure is proposed, featuring a semiconductor layer with a channel portion and conductorization portions, a gate insulator layer with contact holes, and a functional insulating layer. This structure eliminates the need for etching the gate insulator layer, reducing the risk of semiconductor layer damage and allowing for excellent electrical characteristics and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulator layer is etched to form contact holes, then electrical connection is achieved, but the semiconductor layer may be damaged or cut off
Solution Approach 1:
The patent introduces an auxiliary source electrode and auxiliary drain electrode as intermediary elements that establish electrical connection without requiring etching of the gate insulator layer. These auxiliary electrodes serve as mediators between the source/drain electrodes and the semiconductor layer, eliminating direct contact holes through the gate insulator and thus preventing semiconductor layer damage while maintaining reliable electrical connection.
2Reliability
If oxide semiconductor is used to achieve high mobility and transparency, then electrical characteristics improve, but a separate conductorization process is required
Solution Approach 1:
The patent combines the conductorization process with the formation of the auxiliary source and drain electrodes. By integrating these functions into a single process step where the auxiliary electrodes are formed simultaneously with the source and drain electrodes, the separate conductorization process for oxide semiconductor is eliminated, reducing overall process complexity while maintaining the high mobility and transparency benefits of oxide semiconductor.
3Ease of manufacture
If conventional TFT structure is used, then manufacturing is straightforward, but parasitic capacitance cannot be reduced and thin capacitor formation is difficult
Solution Approach 1:
The patent reduces parasitic capacitance by transitioning from a planar configuration to a vertically stacked three-dimensional structure. The auxiliary source and drain electrodes are positioned in different vertical layers relative to the gate electrode, separating their spatial overlap and thereby reducing parasitic capacitance effects while maintaining ease of manufacture through standard thin-film deposition processes.
Data Source
AI summary
Embodiments of the present disclosure relate to a thin film transistor array substrate and display device in which a semiconductor layer has a heterogeneous conductorization structure including heterogeneous conductorization portions having different electrical conductivity, and the gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode part and the gate electrode part and between the drain electrode part and the gate electrode part, so that the possibility of damage to the semiconductor layer can be eliminated or reduced.