Thin-Film Transistor Laser Ablation Channel Patterning
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Solution Overview
Problem
The high cost and photo current issues in the fabrication of thin-film transistors due to the use of multiple photomasks and the sensitivity of amorphous silicon semiconductor materials, which affect the electrical performance and are difficult to repair.
Innovation Solution
A method involving a laser ablation process to define the channel pattern and form source and drain electrodes, reducing the number of photolithography processes and eliminating the need for a half-tone mask for channel pattern definition, thereby lowering fabrication costs and avoiding photo current problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If five photolithography processes are used to fabricate thin-film transistor, then the channel pattern can be defined with good precision, but the fabrication cost increases significantly due to the need for five photomasks
Solution Approach 1:
The patent extracts the channel pattern definition step from the photolithography process and implements it through laser ablation instead. This removes the need for a half-tone mask while maintaining precise channel pattern definition, thereby reducing the total number of photomasks from five to four and lowering fabrication costs
Solution Approach 2:
The patent replaces the optical-based half-tone mask system with a laser ablation system. The laser directly ablates the semiconductor layer to define the channel pattern, substituting the mechanical/optical mask system with a direct energy-based patterning method that achieves similar precision without requiring expensive half-tone masks
2Manufacturing precision
If a half-tone mask is used to define the channel pattern, then the channel pattern can be formed, but the mask formation cost is very high and defects are difficult to repair
Solution Approach 1:
The patent replaces the half-tone mask system with laser ablation. The laser directly patterns the semiconductor layer through controlled ablation, eliminating the need for expensive half-tone masks and their associated alignment and defect issues. This substitution maintains channel pattern precision while dramatically improving manufacturability and reducing defect repair complexity
3Reliability
If source and drain patterns cover the semiconductor layer, then complete electrode coverage is achieved, but photo current is induced due to photo sensitivity of amorphous silicon materials
Solution Approach 1:
The patent extracts the semiconductor layer from beneath the source and drain electrode patterns through selective laser ablation. By removing the photo-sensitive semiconductor material from these regions, the source of photo current generation is eliminated while the electrodes maintain their functional coverage over the channel region
Solution Approach 2:
The patent converts the photo-sensitive property of amorphous silicon from a harmful factor (photo current generation) to a controlled feature. By using laser ablation, the same photo-sensitive material is selectively removed in specific regions where it would cause harm, while preserving it in the channel region where it is needed for transistor operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces fabrication costs and improves the quality of thin-film transistors by eliminating photo current issues and allowing for more stable performance, with fewer photomasks required and no semiconductor layer under data lines, enhancing the overall quality of thin-film transistors.
Implementation Method 1
performing a laser ablation process to define a channel pattern in the four thin films and remove a portion of the second conductive layer
Data Source
AI summary
A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate electrode with the semiconductor layer and the first conductive layer respectively. Then, a laser ablation process is performed to define a channel pattern in the four thin films and remove a portion of the second conductive layer so that unconnected source electrode and drain electrode are formed with the second conductive layer.