Thin Film Transistor Lateral Jumping Connection
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Solution Overview
Problem
Co-planar thin film transistors face issues with poor electrical contact and breakage due to the difficulty in forming connections through deep via holes, leading to uneven active layer thickness and increased production costs, particularly in TFT-LCDs.
Innovation Solution
A thin film transistor design with a flat active layer, source and drain electrodes arranged on the active layer, and a layered structure with insulation layers to facilitate electrical contact and adjustable spacing, reducing the risk of breakage and ensuring uniform thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pixel electrode is electrically connected to the drain electrode via a deep via hole penetrating the passivation layer and gate insulation layer, then electrical contact is achieved, but the pixel electrode is prone to breakage and climbing difficulties occur
Solution Approach 1:
The patent transitions from a vertical deep via hole connection to a lateral jumping connection structure. The pixel electrode extends laterally to contact the drain electrode through an opening in the passivation layer, avoiding the need to climb through deep vertical holes. This dimensional change from vertical to lateral connection resolves the breakage and climbing issues while maintaining electrical contact reliability.
2Strength
If jumping connection is used to realize electrical connection between pixel electrode and drain electrode, then breakage and climbing problems are avoided, but the quantity of masks is increased and production cost is increased
Solution Approach 1:
The patent combines the pixel electrode pattern formation and the jumping connection opening formation into a single photolithography process. The opening in the passivation layer is formed simultaneously with the pixel electrode pattern, eliminating the need for separate masking steps. This merging of processes reduces the number of masks required while maintaining the structural advantages of the jumping connection.
3Ease of manufacture
If the active layer is provided on the source electrode and drain electrode through a lap joint in bottom-gate co-planar TFT, then electrode connection is achieved, but the active layer has uneven thickness and is prone to short circuit
Solution Approach 1:
The patent adopts a top-gate structure where the source and drain electrodes are arranged in the same plane, eliminating the need for the active layer to climb over electrode edges. The gate electrode is positioned above the active layer, creating a vertical field effect transistor structure. This dimensional reorganization allows the active layer to be deposited uniformly across the substrate without thickness variations caused by lap joint formation, preventing short circuits while maintaining ease of manufacture.
Data Source
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AI summary
The present disclosure relates to the field of manufacturing technologies for semiconductor devices and provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor includes: an active layer located on a plane; a source electrode, which is located on the active layer and is in contact with the active layer; a first insulation layer located on the source electrode and including a first via hole; and a drain electrode located on the first insulation layer, where the drain electrode is in contact with the active layer via the first via hole.